Ieee1284 - Brother HL-5130 Service Manual

CHAPTER 3 THEORY OF OPERATION
1.3.3

IEEE1284

Stores the data received from the PC into DRAM as controlled by the DMA controller. It is
applicable to both normal receiving and bi-directional communication (nibble mode, byte
mode, ECP mode).
74LVX161284, 3.3V
connector side
<HL-5130/5140/5150D>
VDD3
INITN
5C
SEINN
5C
HBUSY
5C
STBN
5C
CDCC_D[0]
CDCC_D[1]
CDCC_D[2]
CDCC_D[3]
CDCC_D[4]
CDCC_D[5]
CDCC_D[6]
CDCC_D[7]
CDCC_D[7-0]
3A
<HL-5170DN>
INITN
5D
SEINN
5D
HBUSY
5D
STBN
5D
CDCC_D[0]
CDCC_D[1]
CDCC_D[2]
CDCC_D[3]
CDCC_D[4]
CDCC_D[5]
CDCC_D[6]
CDCC_D[7]
CDCC_D[7-0]
3A
5.0V level shifter IC stores the pull-up resistance in signal wire at the
CDCC_DIR
CDCC_D[7-0]
1C
CDCC_D[0]
CDCC_D[1]
CDCC_D[2]
CDCC_D[3]
CDCC_D[4]
RA7
CDCC_D[5]
10k
CDCC_D[6]
CDCC_D[7]
U5
TP1030
230 245
TP1015
CDCCINITN CDCCACKN
TP1029
229 244
TP1016
CDCCSINN CDCCBUSY
TP1028
228 243
TP1017
CDCCHBUSY CDCCPEN
TP1008
227 242
TP1018
CDCCSTBN CDCCSLCT
241
TP1019
CDCCFLTN
TP1020
240
CDCC_D0
TP1021
239 246
CDCC_D1 CDCC_DIR CDCC_DIR INITN_IN
TP1022
238 250 3A 6B
CDCC_D2 VSCANCLK CDCC_HD SELINN_IN
TP1023
235 3A 6B
CDCC_D3 HBUSY_IN
TP1024
234 6B
CDCC_D4 STBN_IN
TP1025
233 6B
CDCC_D5
TP1026
232
CDCC_D6
TP1027
231
CDCC_D7
Aurora
0V
L PC Printer
H Printer PC
CDCC_DIR
2B
CDCC_HD
2B
0V
CDCC_D[7-0]
1C
CDCC_D[0]
CDCC_D[1]
CDCC_D[2]
CDCC_D[3]
CDCC_D[4]
CDCC_D[5]
CDCC_D[6]
CDCC_D[7]
U7
230 245
CDCCINITN CDCCACKN
229 244
CDCCSINN CDCCBUSY
228 243
CDCCHBUSY CDCCPEN
227 242
CDCCSTBN CDCCSLCT
241
CDCCFLTN
240
CDCC_D0
239
CDCC_D1 INITN_IN
238 CDC-.cir/2B
CDCC_D2 SELINN_IN
CDC-.cir/2B
235
CDCC_D3 HBUSY_IN
234 CDC-.cir/2B
CDCC_D4 STBN_IN
CDC-.cir/2B
233
CDCC_D5
232
CDCC_D6
231
CDCC_D7
Aurora
0V
L PC Printer
H Printer PC
U8
48 18
DIR VCC
3B 1 7
CDCC_HD HD VCC
3B 34 31
GND VCC_CABLE
0V
42
VCC_CABLE
10
GND
15
GND
39
GND
8 41
D[0]
A1 B1
9 40
D[1]
A2 B2
11 38
D[2]
A3 B3
12 37
D[3]
A4 B4
13 36
D[4]
A5 B5
14 35
D[5]
A6 B6
16 33
D[6]
A7 B7
17 32
D[7]
A8 B8
2 47
A9 Y9
3 46
A10 Y10
4 45
A11 Y11
5 44
A12 Y12
6 43
A13 Y13
29 20
C14 A14
28 21
C15 A15
27 22
C16 A16
26 23
C17 A17
19 30
TP998
PLHIN PLH
24 25
HLH HLHIN
TP999
74LVX161284
0V
Fig. 3-7
U11
48 18
DIR VCC VDD3
1 7
HD VCC
34 31
GND VCC_CABLE VDD5
42
VCC_CABLE
10
GND
0V
15
GND
39
GND
8 41
D[0]
A1 B1
9 40
D[1]
A2 B2
11 38
D[2]
A3 B3
12 37
D[3]
A4 B4
13 36
D[4]
A5 B5
14 35
D[5]
A6 B6
16 33
D[6]
A7 B7
17 32
D[7]
A8 B8
2 47
A9 Y9
3 46
A10 Y10
4 45
A11 Y11
5 44
A12 Y12
6 43
A13 Y13
29 20
C14 A14
28 21
C15 A15
27 22
C16 A16
26 23
C17 A17
19 30
PLHIN PLH TP998
24 25
HLH HLHIN
TP999
74LVX161284
0V
Fig. 3-8
3-6
VDD3
VDD5
0V
0V
D[7-0]
6C
TP118
R78
33
HBUSY_IN
TP119
R81
4B
33
SELINN_IN
4B TP120
R85
33
INITN_IN
TP121
4B
R99
33
STBN_IN
4B
DA1
DF5A6.8FU
0V
D[7-0]
6A
TP122
D[0] RA6
33
8
1
D[1]
7
2
D[2]
3 6
D[3]
4 5
D[4] RA5
33
1 8
D[5]
2 7
D[6]
INITN 3 6
TP123
D[7]
2B
SEINN 4 5
2B
HBUSY
DA3
2B
STBN
2B
DF5A6.8FU
0V
0V
D[7-0]
CDC-.cir/3C
TP118
R113
33
HBUSY_IN
TP119
CDC-.cir/1B R115
33
SELINN_IN
TP120
CDC-.cir/1B
R119
33
INITN_IN
TP121
CDC-.cir/1B
R131 33
STBN_IN
CDC-.cir/1B
DA2
DF5A6.8FU
0V
D[7-0]
CDC-.cir/3A
TP122
D[0] RA6
33
1 8
D[1]
2 7
D[2]
3 6
D[3]
4 5
D[4] RA5
33
8
1
D[5]
2 7
D[6]
TP123 3 6
D[7]
4 5
DA4
INITN
DF5A6.8FU
1B
SEINN
0V
1B
HBUSY
1B
STBN
1B
CN6
18
VDD5 +5V
16
0V
17
0V
19
0V
20
0V
21
0V
22
0V
23
0V
24
0V
25
0V
26
0V
27
0V
28
0V
29
0V
30
0V 0V
10
ACK
11
BUSY
12
PE
13
SELECT
32
FLT
14
ATFEED
36
SELIN
31
INPRIM
1
STB
DA2
ZD1
UDZS6.8B
DF5A6.8FU
2
DI1
3
DI2
4
DI3
5
DI4
6
DI5
7
DI6
8
DI7
9
DI8
15
NC NC
DA4
33
NC NC
34
NC NC
35
NC NC
DF5A6.8FU
37
IF_FG FG
38
IF_FG2 FG
CN5
18
+5V
VDD5
16
0V
17
0V
19
0V
20
0V
21
0V
22
0V
23
0V
24
0V
25
0V
26
0V
27
0V
28
0V
29
0V
30
0V 0V
10
ACK
11
BUSY
12
PE
13
SELECT
32
FLT
14
ATFEED
36
SELIN
31
INPRIM
1
STB
DA3
ZD1
UDZS6.8B
DF5A6.8FU
2
DI1
3
DI2
4
DI3
5
DI4
6
DI5
7
DI6
8
DI7
9
DI8
15
NC NC
DA5
33
NC NC
34
NC NC
35
NC
NC
DF5A6.8FU
37
IF_FG FG
38
IF_FG2 FG