Overview Of Operation; Architecture - GE 90*-30 PLC Series User Manual

2

Overview of Operation

Architecture

2-2
The LBIM communicates with other L
LBIM communicates with the PLC CPU over the PLC backplane.
Figure 2-1 provides an overview of the LBIM's architecture. The LBIM has two processors: an
Intel 80186EC processor provides host functions and a 3150 Neuron processor that runs Echelon's
Microprocessor Interface Program (MIP) handles the L
interface is provided by GE Series 90-30 API (application programming interface)
software.
When an input network variable is updated, the data associated with it is copied into the
corresponding PLC input buffer location. The Store Inputs routine is then called to update the
PLC memory during the next PLC scan.
The API (Application Programming Interface) buffers the information for transfer to the PLC
during a subsequent scan. When a scan is received from the PLC, the API initiates a callback, in
which the LBIM's entire PLC output buffer is copied. Each network variable in the output buffer
is then checked to determine whether it differs from the current value of the output buffer. If the
values are different, the network variable is updated over the L
Send Time has been configured, the network variable will not be updated until the Min Send
Time has expired.
The Max Send Time configuration parameter can also drive updating of output network variables
if the value does not change. This assures that, even though data in the source is not changing,
any newly added users will receive a copy and that users also know that the source is still online.
This is how heartbeats are sent across the L
A separate function determines which network variables need updating and forwards the data to
the microprocessor interface program (MIP) through the host interface.
Series 90™-30 PLC LONWORKS® Bus Interface Module User's Manual – June 1997
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GFK-1322A