Horizontal Deflection Signal Processing; System Block Diagram - NEC MultiSync V520 Service Manual

4.

Horizontal deflection signal processing

LM1290:
1. Full-automatic synchronization from 22 kHz to 90 kHz. No component changeover nor external
adjustment is required.
2. DC control H phase and duty cycle.
3. The resistance corresponds to the frequency programmable down to VCO.
4. X-ray input invalid.
5. H-drive invalid due to low VCC (when VCC<9.5V). The H OUT transistor is protected as a result.
6. The capacitor protects the H output transistor during the change of the scanning mode, by means
of the programmable frequency ramming H VO/dt.

System Block Diagram

X-RAY
5
SD
V
14
CC
V
13
8
GND
FVC
11
FILTER
H/HV
3
SYNC
Typical Application LM1290
H
POLARITY
OUTPUT
50k
H/HV
SYNC
INPUT
2k
V
CC
10k
DUTY
5k
CYCLE
CONTROL
1.8V
VOLTAGE
REFERENCE
FCV
V DETECT
H SYNC
2
H/HV POLARITY
20k
1
f
MIN
0.1 µ F
/
H HV
2
POLARITY
/
H HV
3
SYNC
DUTY
4
CYCLE
-
5 X RAY
0.1 µ F
FLYBACK
6
H DRIVE
7
DUTY CNTL
4
DISABLE
LATCH
PD2
S/H VCO
1
10
f
PHASE CNTL
MIN
V
CC
100 µ F
+
470 µ F
+
V
14
CC
0.47 µ F
3.9k
V
REF 13
1 /
PD FILTER
12
VCO IN
4.7nF
+
LM FVC
11
1 µ F
FILTER
1290
PHASE 10
1 µ F
+
PD2
9
FILTER
GND
8
57
H DRIVE
7
9
6
12
PD1
3.3k
H PHASE
5k
CONTROL
V
CC
1.2k
0.1 µ F
H DRIVE
OUTPUT
FLYBACK
PULSE IN
X-RAY
PROTECTION
H DRIVE
PD2
FILTER
FLYBACK
PD1 FILTER/
VCO IN