NEC MultiSync V520 Service Manual page 56

If a low level occurs on the SCL pin in DDC state, the DDC interface will switch to DDC2B state immediately
and set the DDC2B bit to "1". No interrupt will be generated. But, if there is no valid device address and it
receives 128 VSYNC pulses while the SCL is high level, it will lock into DDC2B state and disregard VSYNC.
In some case, program wants to go back DDC1 state, set RDDC bit in REG#1AH and reset it again. This
operation resets the DDC interface to the initial condition.
When it is in DDC2B state, the VSYNC clock is disregarded and the communication protocol follows the
DDC standard. The data format on SDA pin is:
S Address R/W
S: Start condition. A falling edge occurs when SCL is high level.
P: Stop condition. A rising edge occurs when SCL is high level.
A: Acknowledge bit. "0" means acknowledge and "1" means non-ackonwledge.
Address: 7-bit device address.
R/W: Read/Write control bit, "1" is read and "0" is write.
D7, D6, ..., D0: data byte.
The hardware operations in DDC2B state are:
(1) START/STOP detection
When the START condition is detected, the DDC interface Is enabled and set START bit to "1'.
When the STOP condition is detected, the DDC interface is disabled, set STOP bit to "1" and generate
INT0 interrupt.
The START bit is cleared when the following data byte received.
The STOP bit is cleared after writing REG#19H.
(2) Address Recognition
It contains two device addresses in WT6018. On fixed address ('1010000') is for EDID reading and one
programmable address (REG#19H) is for external control, such as auto alignment.
If the address is equal to "1010000", set ADDR bit to"0".
If the address is equal to the bit A6 to bit A0 (REG#19H), set ADDR bit to"1".
If the address is not equal to anyone above, the DDC interface will not response acknowledge.
The ADDR bit is updated when a new device address is received.
(3) Store R/W bit and decide the direction of SDA pin
The R/W bit on the SDA pin will be stored in the RW bit.
(4) Acknowledge bit control/detection
Acknowledge bit control in receive direction:
If ENACK=1 and address compare is true, response acknowledge (Acknowledge bit ="0").
If ENACK=0 or address compare is false, response non-acknowledge (Acknowledge bit ="1").
Acknowledge bit detect in transmit direction:
If the acknowledge bit is "1", the DDC interface will be disabled and release the SDA pin.
If the acknowledge bit is "0", the DDC interface keeps on communicating.
A D7, D6,..., D0 A
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D7, D6,..., D0 A P