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loop
wait
endit
*
link
clr.l
mlove.w
mioveq
asl.l
ori.l
clr.w
mc)ve. b
a:sl. b
move.b
acid.b
a::;l.b
acid.b
a6,IO
d2
16(a6) ,d2
116,dO
dO,d2
I$600000,d2
dl
12 (a6) ,dl
13,dl
14(a6),dO
dO,dl
Il,dl
164,dl
m()vea.l d2,aO
adda.w
dl,aO
m()ve.w
#2
t
dO
equ
*
m()ve.w
(aO) ,dl
bmi
wait
dl>ra
dO,loop
movea.l 8(a6),aO
mc>ve.w
dl, (aO)
unlk
a6
movea.l (sp)+,aO
adlda.w
810,sp
jrnp
(aO)
end
98640A Analog Input Interface
no local storage
get select code
generate a 16 for shift
shift selectcode into place
set the external address bits
get gain
multiply by 8 possible channels
get the channel number
add in channel number
multiply by 2 for word alignment
add in reading register offset
get the base address
add in the register offset
get
3 -
1 counter to clear pipeline
read the card
repeat until busy bit (15) is clear
do this
3
times to clear the pipeline
get the address of value
stuff the value
return to main program
get the return address
clear the stack
return
This routine ignores all readings taken when the busy bit is high. (See the instruction labeled "wait"
and the one after it.) The routine takes three readings in order to push one valid reading through the
pipeline.
(Sel~
the loop that starts at "loop" and continues for the next three instructions.)
Pace Int1erval
You can specify a pace interval by writing a 16-bit value to the pacing register (register address 4).
The value that you write into this register should be
FFF6(hex) - round«period - 0.000018) / 0.0000006)
4-9
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