Conversion Cycle Timing - HP 98640A Installation And Reference Manual

EXTPAC
PACEN
+5
B1JSY
WAIT
GND
GND
PACEN
ENDCT
PACDA
98640A Analog Input Interface
Figure 3-8. AND-OR -INVERT gate (U92)
There are two times during the conversion cycle that the counter can be stopped:
1)
ClocL~~cle~. The PROM sets the WAIT signal high at clock cycle O. If BUSY - is also high, the
output from U92 will go low and cause the counter to stop counting. This situation occurs when
the card is waiting for an analog read. As soon as the CPU removes the card address from the
backplane, BUSY- goes low on the next negative clock transition and U92 releases the counter,
which st.arts counting again on the following positive clock transition.
2)
ClocL~cle-1J.
The PROM sets the PACEN signal high at clock cycle 15. This lets the counter
be stopped by an external pacing circuit or by the pacing timer.
a) An external pacing circuit will stop the counter if it holds the external pacing input of the card
high. This holds EXT PAC low, and the inverted EXTPAC input into U92 stops the counter un-
til the external pacing circuit lets the external pacing input go low again.
b) The internal pacing timer uses the ENDCT signal to stop the counter. In this way, the pacing
timer can stop the conversion cycle to let the programmed pace interval elapse between read-
ings. The pacing timer holds ENDCT high until the timer counts up to FFFF(hex); at that point,
ENDCT goes low and U92 releases the counter. (All this assumes that the PACDA (internal
pace disable) line remains high; this must always be the case except in external pacing situations.
Note that PACDA is controlled by you, not by the card, since it is derived from the internal
pace disable input on terminal 30.)
Conversion Cycle Timing
In the next few paragraphs we will look at the conversion cycle and the way it is controlled by the
signals coming from the PROM. You'll find figure 3-7 usefql for following this discussion. We will
refer to both buffered and unbuffered control signals; keep in mind that buffered signal transitions
actually occur one half cycle after the corresponding unbuffered transitions.
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