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98640A Analog Input Interface
There are three locations that you can legitimately write to: the ID register (for a soft reset), the
status register (to enable interrupts) and the pace timing register (to set the pace interval). We've al-
ready covered the ID register in the discussion of resets, above.
There is only one bit that you can write to in the status register. That is bit 7, the interrupt enable
bit. The output from U97B (valid write) and the decoded status register address (from U69) combine
in U 81 C to produce the STSTAT signal. This clocks bit 7 from the internal address bus into the inter-
rupt enable flip-flop, U93B. The Q output of this flip-flop is wrapped around into bit 7 of the status
register, so that the interrupt enable status is available on a status read.
Writing to the pace timing register is accomplished with the help of the TIME- signal (decoded from
the address by U69) and the "valid write" signal that comes from U97B. These two combine in U81B
to produce t.he signal that clocks the pace timer value from the internal data bus into flip-flops U37
and U49.
Interrupts
The interrupt level of the card is set by two resistors from SIP resistor pack RIO and two switches
from DIP switch pack SW 1, in the same way that the value of the select code is set. The two interrupt
level lines, INTI and INT2, drive bits 4 and S of the status register (U28) so that the interrupt level is
available on a status read. INT I and INT2 also drive the inputs of decoder U79.When interrupts are
enabled by writing to bit 7 of the status register (as discussed above), the interrupt enable flip-flop
(U93B) activates one of the two enable pins of U79. When the BUSY signal goes low, activating the
other enable pin of U79, the appropriate backplane interrupt line (IR3, IR4, IRS, or IR6) goes high,
generating an interrupt to the CPU.
SEQUENCE OF OPERATIONS
What follows is a summary of the operation of the A-to-D card. It is based on the timing diagram for
the conversion cycle, but also includes events from the BUSY cycle. You will probably want to refer
to the timing diagram in Figure 3-7 as you go through the sequence.
In the listing below, the numbers i:n front of each sequence of events indicate the conversion cycle
clock time. Note that the conversion cycle will repeat without stopping only if:
1) the CPU always supplies a new register address (via an analog read) before the Conversion state
machine enters the wait state, and
2) external pacing is not in effect, and
3) the value in the pace timing register is set for the minimum pacing interval (or, alternatively, the
internal pace timer is disabled completely).
If these conditions are not maintained, the Conversion state machine's counter will stop the conversion
cycle; the cycle will remain stopped until the condition that caused it to stop is reversed. (There's
nothing wrong with stopping the conversion counter; in many situations it's positively the right thing
to do. It's just that the timing diagrams look like they keep going continuously and don't stop for
anything.)
In this listing we will mention only "significant" events in the clock cycle. That is, we will not bother
reporting when a signal changes state solely to get back to where it started from.
3-23
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