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98640A Analog Input Interface
Generating Control Signals
The control signals that drive the Conversion state machine are generated by a PROM, U68. The
PROM gets its addresses from counter U98, which is in turn driven by clock generator U 100. The
clock signal to the counter is gated through a NAND gate (U94); this allows the counter to be stopped
when the output of flip-flop U93 is low. The state of U93 is determined by the output of
AND-OR -INVERT gate U92. (The usefulness of this arrangement will become apparent presently.)
When the counter is counting, the address sent to the PROM is incremented with every clock cycle.
For each address, the PROM outputs the bit pattern that was programmed into it; these outputs are
the control signals that drive the conversion circuitry. When the PROM reaches the end of its se-
quence of control signals, it outputs a control signal that resets the counter and causes the sequence to
start over again. The timing diagram in figure 3-7 shows the sequence of control signals generated by
the PROM.
Flip-flop U67 buffers the output of the PROM to remove any glitches that may appear on the output
lines when the outputs change. The PROM outputs are clocked on positive transitions of the system
clock; those signals are clocked into the flip-flop on the negative transition half a clock cycle later.
Since the PROM outputs are unstable only on the positive clock edge, the control signals clocked into
the flip-flop are always clean, and the outputs of the flip-flop are always free of glitches.
The A-to-D card makes use of both buffered and unbuffered control signals. To differentiate be-
tween them, the names of the buffered signals have IIBU II added to the front of the unbuffered signal
name. For instance, the latch signal is named LACH in its unbuffered form and BULACH in its buf-
fered form. The buffered signals are used for most applications on the card, since most devices on the
card use positive clock transitions; use of the negatively clocked buffered signals ensures that the sig-
nals will be waiting at the inputs when the positive clock transition occurs. There are, however, a few
devices on the card that make use of negative clock transitions; unbuffered signals are supplied to the
inputs of these devices.
Stopping the Counter
Each clock cycle takes 600 nanoseconds. Since there are 30 instructions in the control sequence, the
minimum time for completion of the sequence is 18 microseconds. This minimum time is attained
only in certain circumstances; there are some situations in which it is useful to stop the counter and
extend the cycle time.
Stopping the counter is accomplished by the AND-OR-INVERT gate (U92) shown in figure 3-8. The
output of this gate is driven through flip-flop U93 into NAND gate U94. When the output of U92
goes negative, the counter stops.
3-14
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