SOLTEK SL-65ME-T User Manual page 69

Chapter 4 BIOS Setup
SDRAM CAS Latency When synchronous DRAM is installed, the number
Time of clock cycles of CAS latency depends on the
DRAM timing. Do not reset this field from the default
value specified by the system designer.
SDRAM Cycle Time Select the number of SCLKs for an access cycle.
Tras/Trc The choices: 5/7; 7/9
SDRAM RAS-To-CAS This field lets you insert a timing delay between the
Delay CAS and RAS strobe signals, used when DRAM is
written to, read from, or refreshed. Fast gives faster
performance and Slow gives more stable
performance. This field applies only when synchronous
DRAM is installed in the system.
The Choices: 2; 3
SDRAM RAS If an insufficient number of cycles is allowed for the
Precharge Time RAS to accumulate its charge before DRAM refresh,
the refresh may be incomplete and the DRAM may
fail to retain data. Fast gives faster performance;
and Slow gives more stable performance. This field
applies only when synchronous DRAM is installed
in the system.
The Choices: 2; 3
System BIOS Selecting Enabled allows caching of the system
Cacheable BIOS ROM at F0000h-FFFFFh, resulting in better
system performance.
Video BIOS Cacheable Selecting Enabled allows caching of the system
BIOS ROM at C0000h to C7FFFh, resulting in video
performance. However, if any program writes to this
memory area, a system error may result.
Memory Hole At 15M- You can reserve this area of system memory for ISA
16M adapter ROM. When this area is reserved, it cannot
be cached. The user information of peripherals that
need to use this area of system memory usually dis-
cusses their memory requirements.
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