Redboot 80332 Ddr Memory Initialization Sequence - Intel Processor IQ80332 Manual

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Intel IQ80332 I/O Processor
Software Reference
4.3.4

RedBoot 80332 DDR Memory Initialization Sequence

In order to set the correct ECC bits, a DDR memory system (DIMM or discrete components) must be
written to with a known value. This process requires 64-bit writes to the entire DDR memory intended
for use. The following explains the sequence for memory initialization by RedBoot on an 80332 board
with an ECC DIMM. It also includes an example for the scrub (ECC initialization) code.
Initialization Sequence:
1. Disable interrupts. (Technically they are disabled at reset, but for soft reset this is included.
2. Init PBIU (Peripheral Bus Interface Unit) chip selects.
3. Enable I cache.
4. Move Flash to 0xF0000000.
5. Set TTB and Enable MMU.
6. Read DIM for memory parameters.
7. Set Memory Parameters.
8. Delay.
9. Turn DDRAM on.
10. Delay.
11. Enable Data Cache.
12. Enable BTB.
13. Flush all.
14. Clear ECC error logs.
15. Battery Test.
16. Enable ECC.
17. Scrub loop: Write zeros to all memory locations
mov
mov
mov
mov
mov
mov
mov
mov
mov
ldr
// scrub Loop
0:
stmia
subs
bne
50
r8, r4 // save DRAM size
r0, #-1
r1, #-1
r2, #-1
r3, #-1
r4, #-1
r5, #-1
r6, #-1
r7, #-1
r11, = SDRAM_BASE
r11!, {r0-r7}
r12, r12, #32
0
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