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If this number of blocks is greater than the Maximum Pre-fetch Ceiling, then the
number of logical blocks maximally pre-fetched shall be truncated to the value
stored in the Maximum Pre-fetch Ceiling field.
A FSW(Force Sequential Write) bit of one indicates that the controller writes the
multiple block writes to the media in an ascending, sequential, logical block order.
A FSW bit of zero indicates that the controller reorders the sequence of writing
addressed logical blocks in order to achieve a faster command completion.
Since the controller does not support FSW bit, this bit is ignored.
The Disable Read-Ahead(DRA) bit, when one, requests that the device server not
read into the buffer any logical blocks beyond the addressed logical block(s).
When the DRA bit equals zero, the device server may continue to read logical
blocks into the buffer beyond the addressed logical block(s).
The Logical Block Cache Segment Size(LBCSS) bit when one, indicates that the
Cache Segment Size field units shall be interpreted as logical blocks. When the
LBCSS bit equals zero the Cache Segment Size field units shall be interpreted as
butes. The LBCSS shall not impact the units of other field.
The Number of Cache segment specifies how many segments the host requests
that the cache be divided into.
The Cache Segment Size field indicates the requested segment size in bytes. This
standard defines that the Cache Segment Size field is valid only when SIZE bit is
one.
[ Mode Page A
Bit
Byte
0
Reserved
1
2
MODE SELECT:(15h)
5 COMMAND DESCRIPTIONS
]
H
Table 5.48 Control Mode Page (Page Code = A
7
6
5
SPF
0
0
0
0
0
0
Reserved
0
0
0
4
3
Page Code(0A
0
1
Page Length(0A
)
H
0
1
0
0
OEM MANUAL:K6602924
)
H
2
1
0
)
H
0
1
0
0
1
0
GLTSD RLEC
0
0
(cont'd)
Revision: 1 / Date: 2003.03.06
Page: 142 / 273
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