Hitachi ic35l060avv207-0 - Deskstar 60 GB Hard Drive Specifications
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Hitachi ic35l060avv207-0 - Deskstar 60 GB Hard Drive Specifications

3.5 inch ultra ata/100 hard disk drive
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Hard disk drive specifications

Deskstar 180 GXP
3.5 inch Ultra ATA/100 hard disk drive
Models:
IC35L030AVV207
IC35L060AVV207
IC35L090AVV207
IC35L120AVV207
IC35L180AVV207
Revision 4.2
S08-K0000-06
30 April 2003
Publication #2840

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Summary of Contents for Hitachi ic35l060avv207-0 - Deskstar 60 GB Hard Drive

  • Page 1: Hard Disk Drive Specifications

    Hard disk drive specifications Deskstar 180 GXP 3.5 inch Ultra ATA/100 hard disk drive Models: IC35L030AVV207 IC35L060AVV207 IC35L090AVV207 IC35L120AVV207 IC35L180AVV207 Revision 4.2 30 April 2003 S08-K0000-06 Publication #2840...
  • Page 3 Hard disk drive specifications Deskstar 180 GXP 3.5 inch Ultra ATA/100 hard disk drive Models: IC35L030AVV207 IC35L060AVV207 IC35L090AVV207 IC35L120AVV207 IC35L180AVV207 Revision 4.2 30 April 2003 S08-K0000-06 Publication #2840...
  • Page 4 It is possible that this publication may contain reference to, or information about, Hitachi products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Hitachi intends to announce such Hitachi products, programming, or services in your country.

  • Page 5: Table Of Contents

    Table of contents List of figures ..............1.0 General .
  • Page 6 6.5.1 Input voltage ............6.5.2 Power supply current (typical) .
  • Page 7 9.0 General operation ............9.1 Reset response .
  • Page 8 11.3 Execute Device Diagnostic (90h) ..........11.4 Flush Cache (E7h) .
  • Page 9 11.42.6 Self-test log data structure ..........11.42.7 Error reporting .
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  • Page 11: List Of Figures

    List of figures Figure 1. Formatted capacity ............Figure 2.
  • Page 12 Figure 53. Input voltage ............Figure 54.
  • Page 13 Figure 108. Idle Immediate Command (E1h/95h) ........Figure 109.
  • Page 14 Figure 164. SMART summary error log sector ........Figure 165.

  • Page 15: General

    1.0 General This document describes the specifications of the Deskstar 180GXP, an IBM 3.5-inch 7200-rpm ATA interface hard disk drive with the following model numbers: IC35L030AVV207- 0 (30.7 GB, 2-MB buffer) IC35L060AVV207- 0 (41.2 GB and 60.4 GB, 2-MB buffer) IC35L090AVV207- 0 (82.3 GB, 2-MB buffer) IC35L090AVV207- 1...
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  • Page 17: General Features

    2.0 General features Data capacities of 30 GB - 180 GB Spindle speeds of 7200 RPM Fluid Dynamic Bearing motor Enhanced IDE interface Sector format of 512 bytes/sector Closed-loop actuator servo Load/Unload mechanism Automatic Actuator lock Interleave factor 1:1 Seek time of 8.8 ms (30-GB, 40-GB, and 60-GB models), 8.5 ms (all other models) in Read Operation Seek time of 8.5 ms (30-GB, 40-GB, and 60-GB models), 8.2 ms (all other models) typical without Command Overhead)
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  • Page 19: Part 1. Functional Specification

    Part 1. Functional specification Deskstar 180GXP hard disk drive specifications...
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  • Page 21: Fixed Disk Subsystem Description

    3.0 Fixed disk subsystem description 3.1 Control Electronics The drive is electronically controlled by a microprocessor, several logic modules, digital/analog modules, and various drivers and receivers. The control electronics performs the following major functions: Controls and interprets all interface signals between the host controller and the drive. Controls read write accessing of the disk media, including defect management and error recovery.
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  • Page 23: Drive Characteristics

    4.0 Drive characteristics This section describes the characteristics of the drive. 4.1 Default logical drive parameters The default of the logical drive parameters in Identify Device data is as shown below. IC35L060AVV207 Description IC35L030AVV207 IC35L060AVV207 IC35L060AVV207 Optimized 40 GB Physical Layout Label capacity (GB) Bytes per Sector Sectors per Track...

  • Page 24: Data Sheet

    4.2 Data sheet Description Data transfer rate (Mbps) [Data transfer rate (Mbps) - optimized 40 GB] Interface transfer rate (MB/s) 2,048 Data buffer size Data buffer size Models IC35L090AVV207-1, 8,192 IC35L120AVV207-1, IC35L180AVV207-1 Rotational speed (RPM) 7,200 Number of buffer segments (read) up to 21 Number of buffer segments (write) up to 63...

  • Page 25: Drive Organization

    This cylinder contains the user data which can be sent and retrieved via read/write commands and a spare area for reassigned data. Spare cylinder The spare cylinder is used by Hitachi Globobal Storage Technologies manufacturing and includes data sent from a defect location. Deskstar 180GXP hard disk drive specifications...

  • Page 26: Performance Characteristics

    4.4 Performance characteristics Drive performance is characterized by the following parameters: Command overhead Mechanical positioning - Seek time - Latency Data transfer speed Buffering operation (Look ahead/Write cache) All the above parameters contribute to drive performance. There are other parameters that contribute to the performance of the actual system.

  • Page 27: Figure 6. Full Stroke Seek Time

    The terms “Typical” and “Max” are used throughout this specification with the following meanings: Typical. The average of the drive population tested at nominal environmental and voltage con- ditions. Max. The maximum value measured on any one drive over the full range of the environmental and voltage conditions.

  • Page 28: Drive Ready Time

    4.4.2.4 Cylinder switch time (Cylinder skew) Cylinder switch time - typical (ms) 72 kTPI Figure 8. Cylinder switch time Cylinder switch time is defined as the amount of time required by the fixed disk to access the next sequential block after reading the last sector in the current cylinder. The measuring method is given in Section 4.4.5, “Throughput”...

  • Page 29: Data Transfer Speed

    4.4.4 Data transfer speed 180 GB model Data transfer speed (Mbyte/s) Disk-Buffer transfer (Zone 0) Instantaneous - typical Sustained - read typical 56.3 Disk-Buffer transfer (Zone 26) Instantaneous - typical 34.5 Sustained - read typical 29.4 Buffer-Host (max) Figure 12. Data transfer speed Instantaneous disk-buffer transfer rate (Mbyte/s) is derived by the following formula: 512 (Number of sectors on a track) (revolution per second) Note: The number of sectors per track will vary because of the linear density recording.

  • Page 30: Throughput

    4.4.5 Throughput 4.4.5.1 Simple sequential access The following figure illustrates the case of the three-disk enclosure. Operation Typical (sec) Max (sec) Sequential Read (Zone 0) 0.32 0.34 Sequential Read (Zone 26) 0.61 0.64 Figure 13. Simple Sequential Access performance The above table gives the time required to read a total of 8000h consecutive blocks (16,777,216 bytes) accessed by 128 read commands.

  • Page 31: Operating Modes

    Operating mode Description Start up time period from spindle stop or power down Spin-up Seek operation mode Seek Write operation mode Write Read operation mode Read Spindle rotation at 7200 RPM with heads unloaded Unload Idle Spindle motor and servo system are working normally. Commands can be re- Idle ceived and processed immediately Actuator is unloaded and spindle motor is stopped.
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  • Page 33: Defect Flagging Strategy

    5.0 Defect flagging strategy Media defects are remapped to the next available sector during the Format Process in manufacturing. The mapping from LBA to the physical locations is calculated by an internally maintained table. Shipped format Data areas are optimally used. No extra sector is wasted as a spare throughout user data areas.
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  • Page 35: Specification

    6.0 Specification 6.1 Electrical interface 6.1.1 Connector location Refer to the following illustration to see the location of the connectors. Figure 17. Connector location (2- and 3-disk model shown) 6.1.1.1 DC power connector The DC power connector is designed to mate with AMP part number 1-480424-0 using AMP pins part number 350078-4 (strip), part number 61173-4 (loose piece), or their equivalents.

  • Page 36: Signal Definition

    6.1.2 Signal definition The pin assignments of interface signals are listed in the figure below: SIGNAL Type SIGNAL Type RESET- 3-state 3-state 3-state 3-state 3-state DD10 3-state 3-state DD11 3-state 3-state DD12 3-state 3-state DD13 3-state 3-state DD14 3-state 3-state DD15 3-state (20)
  • Page 37 Address used to select the individual register in the drive. DA0-DA2 Chip select signal generated from the Host address bus. When active, one of the CS0- Command Block Registers (Data, Error {Features when written}, Sector Count, Sector Number, Cylinder Low, Cylinder High, Drive/Head and Status {Command when written} register) can be selected.
  • Page 38 The drive is configured as either Device 0 or 1 depending upon the value of CSEL. If CSEL is grounded, the device address is 0 If CSEL is open, the device address is 1 Pin position 20 has no connection pin. It is recommended to close the respective position of the cable connector in order to avoid incorrect insertion by mistake.

  • Page 39: Interface Logic Signal Levels

    The termination resistors on the device side are implemented on the drive side as follows: 33 Ω for DD0 thru DD15, DMARQ, INTRQ 82 Ω for CS0-, CS1-, DA0, DA1, DA2, DIOR-, DIOW-, DMACK- 22 Ω for IORDY 6.1.3 Interface logic signal levels The interface logic signal has the following electrical specifications: Input High Voltage 2.0 V min.

  • Page 40: Signal Timings

    6.2 Signal timings 6.2.1 Reset timings Drive reset timing. RESET- BUSY Figure 21. System reset timing chart PARAMETER DESCRIPTION Min (usec) Max (sec) RESET low width RESET high to not BUSY – Figure 22. System reset timing Deskstar 180GXP hard disk drive specifications...

  • Page 41: Pio Timings

    6.2.2 PIO timings The PIO cycle timings meet Mode 4 of the ATA/ATAPI-6 description. CS(1:0) DA(2:0) DIOR-, DIOW- Write data DD(15:0) Read data DD(15:0) IORDY (*) Up to ATA-2 (mode-0,1,2) Figure 23. PIO cycle timings chart PARAMETER DESCRIPTION MIN (ns) MAX (ns) Cycle time –...

  • Page 42: Read Drq Interval Time

    6.2.2.2 Read DRQ interval time For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows: In the event that a host reads the status register only before the sector or block transfer DRQ interval, the DRQ interval 4.2 µs In the event that a host reads the status register after or both before and after the sector or block transfer, the DRQ interval is 11.5 µs...

  • Page 43: Multiword Dma Timings

    6.2.3 Multiword DMA timings The Multiword DMA timing meets Mode 2 of the ATA/ATAPI-6 description. CS0-/CS1- tLR/tLW DMARQ DMACK- tKR/tKW DIOR-/DIOW- READ DATA WRITE DATA Figure 25. Multiword DMA cycle timing chart PARAMETER DESCRIPTION MIN (ns) MAX (ns) Cycle time –...

  • Page 44: Ultra Dma Timings

    6.2.4 Ultra DMA timings The Ultra DMA timing meets Mode 0,1,2,3 4, and 5 of the Ultra DMA Protocol. 6.2.4.1 Initiating Read DMA DMARQ DMACK- tACK tENV STOP tACK tENV t2CYC HDMARDY- tCYC tCYC tZIORDY tDZFS DSTROBE tZAD DD(15:00) xxxxxxxxxxxxxxxxxxxxxxxxx RD Data RD Data RD Data...

  • Page 45: Figure 29. Ultra Dma Cycle Timing Chart (Host Pausing Read)

    6.2.4.2 Host Pausing Read DMA DMARQ DMACK- STOP HDMARDY- tRFS DSTROBE Figure 29. Ultra DMA cycle timing chart (Host pausing Read) MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 PARAMETER DESCRIPTION (all values in ns) DSTROBE to HDMARDY– time – – – –...

  • Page 46: Figure 31. Ultra Dma Cycle Timing Chart (Host Terminating Read)

    6.2.4.3 Host Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tRFS tIORDYZ DSTROBE DD(15:00) xxxxxxxxxx xxx RD Data xxxxxxxxxxxxxxxxxx tZAH Device drives DD Host drives DD Figure 31. Ultra DMA cycle timing chart (Host terminating Read) MODE0 MODE1 MODE2 MODE3 MODE4...

  • Page 47: Figure 33. Ultra Dma Cycle Timing Chart (Device Terminating Read)

    6.2.4.4 Device Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tIORDYZ DSTROBE DD(15:00) xxxxx xxxxxxxxxx xxxxxxxxxxxxxxxxxx tZAH Host drives DD Device drives DD Figure 33. Ultra DMA cycle timing chart (Device terminating Read) MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 PARAMETER DESCRIPTION (all values in ns)

  • Page 48: Figure 35. Ultra Dma Cycle Timing Chart (Initiating Write)

    6.2.4.5 Initiating Write DMA DMARQ DMACK- tENV tACK STOP tZIORDY t2CYC DDMARDY- tACK tCYC tCYC HSTROBE DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx WT Data WT Data WT Data Host drives DD Figure 35. Ultra DMA cycle timing chart (Initiating Write) MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 PARAMETER DESCRIPTION...

  • Page 49: Figure 37. Ultra Dma Cycle Timing Chart (Device Pausing Write)

    6.2.4.6 Device Pausing Write DMA DMARQ DMACK- STOP DDMARDY- tRFS HSTROBE Figure 37. Ultra DMA cycle timing chart (Device Pausing Write) MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 PARAMETER DESCRIPTION (all values in ns) HSTROBE to DDMARDY– – – – – –...

  • Page 50: Figure 39. Ultra Dma Cycle Timing Chart (Device Terminating Write)

    6.2.4.7 Device Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK tRFS HSTROBE DD(15:00) xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx xxx WT Data Host drives DD Figure 39. Ultra DMA cycle timing chart (Device Terminating Write) MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 PARAMETER DESCRIPTION (all values in ns) DDMARDY to final HSTROBE...

  • Page 51: Figure 41. Ultra Dma Cycle Timing Chart (Host Terminating Write)

    6.2.4.8 Host Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK HSTROBE DD(15:00) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx Host drives DD Figure 41. Ultra DMA cycle timing chart (Host Terminating Write) MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 PARAMETER DESCRIPTION (all values in ns) Time from HSTROBE to edge –...

  • Page 52: Addressing Of Registers

    6.2.5 Addressing of registers The host addresses the drive through a set of registers called the Task File. These registers are mapped into the I/ O space of the host. Two chip select lines (CS0– and CS1–) and three address lines (DA0-02) are used to select one of these registers, while a DIOR–...

  • Page 53: Jumper Settings

    6.3 Jumper settings 6.3.1 Jumper pin location Jumper pins Figure 44. Jumper pin location (2- and 3-disk model shown) 6.3.2 Jumper pin identification Pin I Pin A DERA001.prz Pin B Figure 45. Jumper pin identification (2- and 3-disk model shown) Deskstar 180GXP hard disk drive specifications...

  • Page 54: Jumper Pin Assignment

    6.3.3 Jumper pin assignment There are four jumper settings as shown in the following sections: 16 logical head default (normal use) 15 logical head default 2 GB/32 GB clip Power up in standby Within each of these four jumper settings the pin assignment selects Device 0, Device 1, Cable Selection, or Device 1 Slave Present as shown in the following figures.

  • Page 55: Jumper Positions

    6.3.4 Jumper positions 6.3.4.1 16 logical head default (normal use) The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device 1 (Slave) Present. DEVICE 0 (Master) DEVICE 1 (Slave) CABLE SEL DEVICE 1 (Slave) Present Shipping Default Condition (DEVICE 0)

  • Page 56: Figure 48. Jumper Positions For 15 Logical Head Default

    6.3.4.2 15 logical head default The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device 1 (Slave) Present setting 15 logical heads instead of default 16 logical head models. DEVICE 0 (Master) DEVICE 1 (Slave) CABLE SEL DEVICE 1 (Slave) Present...

  • Page 57: Figure 49. Jumper Positions For Capacity Clip To 2Gb/32Gb

    6.3.4.3 Capacity clip to 2GB/32GB The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device 1 (Slave) Present while setting the drive capacity down either to 2 GB or 32 GB for the purpose of compatibility.

  • Page 58: Figure 50. Jumper Settings For Disabling Auto Spin

    6.3.4.4 Power Up In Standby The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device 1 (Slave) Present to enable Power Up In Standby. DEVICE 0 (Master) DEVICE 1 (Slave) CABLE SEL DEVICE 1 (Slave) Present Figure 50.

  • Page 59: Environment

    6.4 Environment 6.4.1 Temperature and humidity Operating conditions Temperature 5 to 55°C Relative humidity 8 to 90% non-condensing Maximum wet bulb temperature 29.4°C non-condensing Maximum temperature gradient 15°C/Hour Altitude –300 to 3,048 m Non-Op conditions Temperature -40 to 65°C Relative humidity 5 to 95% non-condensing Maximum wet bulb temperature 35°C non-condensing...

  • Page 60: Corrosion Test

    Environment Specification 36C/95% 31C/90% Wet Bulb 35C Wet Bulb 29.4C Nonoperating Operating 65C/14% 55C/15% Temperature (C) Figure 52. Limits of temperature and humidity Note: Storage temperature range is 0° to 65°. 6.4.2 Corrosion test The drive shows no sign of corrosion inside and outside of the hard disk assembly and is functional after being subjected to seven days at 50°C with 90% relative humidity.

  • Page 61: Dc Power Requirements

    6.5 DC power requirements The following voltage specifications apply at the power connector of the drive. Damage to the drive electronics may result if the power supply cable is connected or disconnected while power is being applied to the drive (no hot plug/unplug is allowed). Connections to the drive should be made in a low voltage, isolated secondary circuit (SELV).

  • Page 62: Figure 55. Power Supply Current Of 80 Gb And 120 Gb Models

    Power supply current of +5 Volts [mA] +12 Volts [mA] Total 120-GB and 80-GB models Pop Mean Std Dev Pop Mean Std Dev (values in milliamps. RMS) Idle average Idle ripple (peak-to-peak) Low RPM Idle Low RPM Idle Ripple Unload Idle average Unload Idle Ripple Seek average Seek peak...

  • Page 63: Power Supply Generated Ripple At Drive Power Connector

    6.5.3 Power supply generated ripple at drive power connector Maximum (mV pp) +5V DC 0-10 +12V DC 0-10 Figure 57. Power supply generated ripple at drive power connector During drive start up and seeking 12-volt ripple is generated by the drive (referred to as dynamic loading). If the power of several drives is daisy chained together, the power supply ripple plus the dynamic loading of the other drives must remain within the above regulation tolerance.

  • Page 64: Reliability

    6.6 Reliability 6.6.1 Data integrity No more than one sector is lost at Power loss condition during the write operation when the write cache option is disabled. If the write cache option is active, the data in write cache will be lost. To prevent the loss of customer data, it is recommended that the last write access before power off be issued after setting the write cache off.

  • Page 65: Mechanical Specifications

    6.7 Mechanical specifications 6.7.1 Physical dimensions 25.4 } 0.4 101.6 } 0.4 } 0.6 BREATHER HOLE (*) Dia. 2.0 } 0.1 38.9 } 0.4 19.7 LEFT FRONT * DO NOT BLOCK THE BREATHER HOLE. Figure 58. Top and side views of 80 GB - 180 GB models with mechanical dimensions All dimensions are in millimeters.

  • Page 66: Figure 59. Bottom And Side Views Of 30Gb - 60Gb Models With Breather Hole And

    BREATHER HOLE Figure 59. Bottom and side views of 30GB - 60GB models with breather hole and mounting hole locations All dimensions in the above figure are in millimeters. The breather hole must be kept uncovered in order to keep the air pressure inside of the disk enclosure equal to external air pressure.

  • Page 67: Hole Locations

    6.7.2 Hole locations The mounting hole location and size of the drive are shown below. (6X) Max. penetration 4.5 mm Side View I/F Connector Bottom View (4X) Max. penetration 4.0 mm Thread 6-32 UNC 41.28±0.5 44.45±0.2 95.25±0.2 6.35±0.2 28.5±0.5 60.0±0.2 41.6±0.2 Figure 61.

  • Page 68: Connector Locations

    6.7.3Connector locations Figure 62. Connector locations 6.7.4 Drive mounting The drive will operate in all axes (6 directions). Performance and error rate will stay within specification limits if the drive is operated in the other orientations from which it was formatted. For reliable operation, the drive must be mounted in the system securely enough to prevent excessive motion or vibration of the drive during seek operation or spindle rotation, using appropriate screws or equivalent mounting hardware.

  • Page 69: Vibration And Shock

    6.8 Vibration and shock All vibration and shock measurements recorded in this section are made with a drive that has no mount- ing attachments for the systems. The input power for the measurements is applied to the normal drive mounting points. 6.8.1 Operating vibration 6.8.1.1 Random vibration The hard disk drive meets IBM Standard C-S 1-9711-002 (1990-03) for the V5L applied to horizontal...

  • Page 70: Operating Shock

    6.8.2.2 Swept sine vibration 2 G (Zero to peak), 5 to 500 to 5 Hz sine wave 0.5 oct/min sweep rate 3 minutes dwell at two major resonances 6.8.3 Operating shock The drive meets IBM Standard C-S 1-9711-007 for the S5 product classification. The drive meets the following criteria while operating in the conditions described below.

  • Page 71: Acoustics

    6.9 Acoustics The upper limit criteria of the octave sound power levels are given in Bels relative to one picowatt and are shown in the following table. The sound power emission levels are measured in accordance with ISO 7779. Typical / Max 60-GB, 40GB, Mode 120-GB and...

  • Page 72: Identification Labels

    6.10 Identification labels The following labels are affixed to every drive shipped from the drive manufacturing location in accord- ance with the appropriate hard disk drive assembly drawing: A label containing the IBM logo, the IBM part number, and the statement “Made by IBM Japan Ltd.” or IBM approved equivalent A label containing the drive model number, the manufacturing date code, the formatted capacity, the place of manufacture, UL/CSA/TUV/CE/C-Tick mark logos...

  • Page 73: Safety

    6.11 Safety 6.11.1 UL and CSA standard conformity The product is qualified per UL 1950 Third Edition and CAN/CSA C22.2 No. 950-M95, Third Edition, for use in Information Technology Equipment including Electric Business Equipment. The UL recognition or the CSA certification is maintained for the product life. The UL and C-UL recognition mark or the CSA monogram for CSA certification appear on the drive.

  • Page 74: Electromagnetic Compatibility

    The product is declared to be in conformity with requirements of the following EC directives under the sole responsibility of Hitachi Global Storage Technologies Japan, Ltd. Council Directive 89/336/EEC on the approximation of laws of the Member States relating to electromagnetic compatibility.

  • Page 75: Part 2. Interface Specification

    Part 2. Interface specification Deskstar 180GXP hard disk drive specifications...
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  • Page 77: General

    7.0 General This specification describes the host interface of the Deskstar 180GXP hard disk drive. The interface conforms to the Working Document of Information Technology - AT Attachment with Packet Interface Extension (ATA/ATAPI-6), Revision 3b, dated 26 February 2002, with deviations as described in Section 7.2, “Deviations from standard”...
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  • Page 79: Registers

    8.0 Registers Addresses Functions CS0– CS1– READ (DIOR–) WRITE (DIOW–) Data bus high impedance Not used Control block registers Data bus high impedance Not used Data bus high impedance Not used Alternate Status Device Control Device Address Not used Command block registers Data Data Error Register...

  • Page 80: Alternate Status Register

    8.1 Alternate Status Register Alternate Status Register DSC/ SERV Figure 69. Alternate Status Register This register contains the same information as the Status Register. The only difference is that reading this register does not imply interrupt acknowledge or clear a pending interrupt. See 8.13, “Status Register” on page 70 for the definition of the bits in this register.

  • Page 81: Data Register

    8.5 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers which are 8 bits wide.

  • Page 82: Device/Head Register

    -H3,-H2,-H1,-H0 - -Head Select. These four bits are the 1's complement of the binary coded address of the currently selected head. -H0 is the least significant. -Drive Select 1. Drive select bit for device 1, active low. DS1=0 when device 1 (slave) is -DS1 selected and active.

  • Page 83: Features Register

    Bit Definitions Interface CRC Error. CRC=1 indicates a CRC error has occurred on the data bus ICRCE during Ultra-DMA transfer. (CRC) Uncorrectable Data Error. UNC=1 indicates an uncorrectable data error has been encountered. ID Not Found. IDN=1 indicates the ID field of the requested sector could not be found. IDNF (IDN) Aborted Command.

  • Page 84: Status Register

    8.13 Status Register Status Register DSC/ DRDY CORR SERV Figure 74. Status Register This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command. If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknow- ledge.

  • Page 85: General Operation

    9.0 General operation 9.1 Reset response There are three types of resets in ATA: Power On Reset (POR). The device executes a series of electrical circuitry diagnostics, spins up the HDA, tests speed and other mechanical parameters, and sets default values. Hard Reset (Hardware Reset).

  • Page 86: Register Initialization

    9.1.1 Register initialization After power on, hard reset, or software reset, the register values are initialized as shown in the figure below. Register Default Value Error Diagnostic Code Sector Count Sector Number Cylinder Low Cylinder High Device/Head Status Alternate Status Figure 76.

  • Page 87: Diagnostic And Reset Considerations

    9.2 Diagnostic and reset considerations For each Reset and Execute Device Diagnostic the diagnostic is done as follows: Power On Reset. DASP- is read by Device 0 to determine if Device 1 is present. If Device 1 is present, Device 0 shall read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error.

  • Page 88: Sector Addressing Mode

    9.3 Sector Addressing Mode All addressing of data sectors recorded on the drive media is by a logical sector address. The logical CHS address for the drive is different from the actual physical CHS location of the data sector on the disk media.

  • Page 89: Overlapped And Queued Feature

    9.4 Overlapped and queued feature Overlap allows devices to perform a bus release so that the other device on the bus may be used. To perform a bus release the device clears both DRQ and BSY to zero. When selecting the other device during overlapped operations, the host shall disable interrupts via the nIEN bit on the currently selected device before writing the Device/Head register to select the other device.

  • Page 90: Power Management Feature

    9.5 Power management feature The power management feature set permits a host to reduce the power required to operate the drive. It provides a set of commands and a timer that enable a device to implement low power consumption modes. The drive implements the following set of functions: Standby timer Idle command...

  • Page 91: Interface Capability For Power Modes

    9.5.4 Interface capability for power modes Each power mode affects the physical interface as defined in the following table. Interface Mode Media active Active Active Idle Active Standby Inactive Sleep Inactive Figure 79. Power conditions Ready (RDY) is not a power condition. A device may post ready at the interface even though the media may not be accessible.

  • Page 92: Function

    9.6 S.M.A.R.T. function The intent of Self-Monitoring Analysis and Reporting Technology (S.M.A.R.T) is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, S.M.A.R.T devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault condition.

  • Page 93: Self-Test

    disabled. Disabling SMART disables the delivering of error log information via the SMART READ LOG SECTOR command. If a device receives a firmware modification, all error log data is discarded and the device error count for the life of the device is reset to zero. 9.6.8 Self-test The device provides the self-test features which are initiated by SMART Execute Off-line Immediate command.

  • Page 94: Security Mode Feature Set

    9.7 Security Mode Feature Set Security Mode Feature Set is a powerful security feature. With a device lock password, a user can pre- vent unauthorized access to a hard disk device even if the device is removed from the computer. The following commands are supported for this feature: ('F1'h) Security Set Password...

  • Page 95: Operation Example

    The system manufacturer or dealer who intends to enable the device lock function for end-users must set the master password even if only single level password protection is required. 9.7.4 Operation example 9.7.4.1 Master Password setting The system manufacturer or dealer can set a new Master Password from default Master Password using the Security Set Password command without enabling the Device Lock Function.

  • Page 96: Figure 81. Usual Operation

    9.7.4.3 Operation from POR after User Password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed. Device Locked mode Unlock CMD Erase Prepare Media Access Non-media access Command (*1) Command (*1) Erase Unit...

  • Page 97: Figure 82. Password Lost

    9.7.4.4 User Password Lost If the User Password is forgotten and High level security is set, the system user cannot access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.

  • Page 98: Command Table

    9.7.5 Command table This table shows the response of the device to commands when the Security Mode Feature Set (Device lock function) is enabled. Command Locked Mode Unlocked Mode Frozen Mode Check Power Mode Executable Executable Executable Execute Device Diagnostic Executable Executable Executable...

  • Page 99: Figure 84. Command Table For Device Lock Operation (Part 2 Of 2)

    Command Locked Mode Unlocked Mode Frozen Mode Seek Executable Executable Executable Service Command aborted Executable Executable Set Features Executable Executable Executable Set Max Address Command aborted Executable Executable Set Max Address Ext Command aborted Executable Executable Set Multiple Mode Executable Executable Executable Sleep...

  • Page 100: Host Protected Area Function

    9.8 Host Protected Area Function The Host Protected Area Function provides a protected area which cannot be accessed via conventional methods. This protected area is used to contain critical system data such as BIOS or system manage- ment information. The contents of the main memory of the entire system may also be dumped into the protected area to resume after system power off.

  • Page 101: Security Extensions

    4. Advanced usage using protected area The data in the protected area is accessed by the following method: Issue Read Native Max Address command to get the real device maximum LBA. Returned value shows that native device maximum LBA is 12,692,735 (C1ACFFh) regardless of the current setting.

  • Page 102: Seek Overlap

    9.9 Seek Overlap The Deskstar 180GXP provides an accurate method for measuring seek time. The seek command is usually used to measure the device seek time by accumulating the execution time for a number of seek commands. With typical implementation of seek command this measurement must include the device and host command overhead.

  • Page 103: Write Cache Function

    9.10 Write cache function Write cache is a performance enhancement whereby the device reports the completion of the write com- mand (Write Sectors, Write Multiple, and Write DMA) to the host as soon as the device has received all of the data into its buffer.

  • Page 104: Power-Up In Standby Feature Set

    9.12 Power-Up In Standby feature set The Power-Up In Standby feature set allows devices to be powered-up into the Standby power manage- ment state to minimize inrush current at power-up and to allow the host to sequence the spin-up of devices.

  • Page 105: Automatic Acoustic Management Feature Set (Aam)

    9.14 Automatic Acoustic Management feature set (AAM) This feature set allows the host to select an acoustic management level. The acoustic management level may range from the lowest acoustic emanation setting of 01h to the maximum performance level of FEh. Device performance and acoustic emanation may increase with increasing acoustic management levels.

  • Page 106: Identify Device Data

    Before Enable Address Offset Mode A reserved area has been created using a nonvolatile Set Max command. Non-Accessible Accessible (System reserved (User Area) area) LBA 0 LBA R LBA M After Enable Address Offset Mode Accessible Non-Accessible (System reserved (User area) area) LBA 0 LBA M–R...

  • Page 107: 48-Bit Address Feature Set

    9.16 48-bit Address Feature Set The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This allows device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that may be transferred by a single command are increased by increasing the allowable sector count to 16 bits. Commands unique to the 48-bit Address feature set are Flush Cache Ext Read DMA Ext...
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  • Page 109: Command Protocol

    10.0 Command Protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check if BSY=1, and should proceed no further unless and until BSY=0.

  • Page 110: Pio Data In Commands

    10.1 PIO Data In commands These commands are Device Configuration Identify Identify Device Read Buffer Read Log Ext Read Long Read Multiple Read Multiple Ext Read Sector(s) Read Sector(s) Ext S.M.A.R.T. Read Attribute Values S.M.A.R.T. Read Attribute Thresholds S.M.A.R.T. Read Log Sector Execution includes the transfer of one or more 512 byte (>512 bytes on Read Long) sectors of data from the device to the host.
  • Page 111 Note that the status data for a sector of data is available in the Status Register before the sector is trans- ferred to the host. If the device detects an invalid parameter, it will abort the command by setting BSY=0, ERR=1, ABT=1, and interrupting the host.

  • Page 112: Pio Data Out Commands

    10.2 PIO Data Out commands These commands are PIO Data Out commands: Device Configuration Set Format Track Security Disable Password Security Erase Unit Security Set Password Security Unlock Set Max Set Password command Set Max Unlock command SMART Write Log Sector Write Buffer Write Log Ext Write Long...
  • Page 113 f. The device clears the interrupt in response to the Status Register being read. The Write Multiple command transfers one block of data for each interrupt. The other commands transfer one sector of data for each interrupt. If the device detects an invalid parameter, it will abort the command by setting BSY=0, ERR=1, ABT=1, and interrupting the host.

  • Page 114: Non-Data Commands

    10.3 Non-data commands The following are non-data commands: Check Power Mode Device Configuration Freeze Lock Device Configuration Restore Execute Device Diagnostic Flush Cache Flush Cache Ext Idle Idle Immediate Initialize Device Parameters Read Native Max Address Read Native Max Address Ext Read Verify Sector(s) Read Verify Sector(s) Ext Recalibrate...
  • Page 115 4. When the device has finished processing the command, it sets BSY=0 and interrupts the host. 5. In response to the interrupt, the host reads the Status Register. 6. The device clears the interrupt in response to the Status Register being read. Deskstar 180GXP hard disk drive specifications...

  • Page 116: Dma Commands

    10.4 DMA commands DMA commands are Read DMA Read DMA Ext Write DMA Write DMA Ext Data transfers using DMA commands differ in two ways from PIO transfers: data transfers are performed using the slave DMA channel no intermediate sector interrupts are issued on multisector commands Initiation of the DMA transfer commands is identical to the Read Sector(s) or Write Sector(s) commands except that the host initializes the slave-DMA channel prior to issuing the command.

  • Page 117: Dma Queued Commands

    10.5 DMA queued commands DMA queued commands are Read DMA Queued Read DMA Queued Ext Service Write DMA Queued Write DMA Queued Ext 1. Command Issue a. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers.
  • Page 118 This page intentionally left blank.

  • Page 119: Command Descriptions

    11.0 Command descriptions Commands marked * are alternate command codes for the previously defined command. See the next page for list of Protocol definitions. Binary Code Bit Code Protocol Command (Hex) Check Power Mode Check Power Mode* Device Configuration Restore Device Configuration Freeze Lock Device Configuration Identify Device Configuration Set...

  • Page 120: Figure 88. Command Set (2 Of 2)

    Binary Code Bit Code Protocol Command (Hex) Security Set Password Security Unlock Seek Service Set Features Set Max Address Set Max Address Ext Set Multiple Mode Sleep Sleep* SMART Disable Operations SMART Enable/Disable Attribute Auto save SMART Enable Operations SMART Execute Off-line Data Collection SMART Read Attribute Values SMART Read Attribute Thresholds SMART Return Status...

  • Page 121: Figure 89. Command Set (Subcommands)

    Command code Feature Command (Subcommand) (Hex) Register (Hex) (S.M.A.R.T Function) SMART Read Attribute Values SMART Read Attribute Thresholds SMART Enable/Disable Attribute Autosave SMART Save Attribute Values SMART Execute Off-line Data Collection SMART Read Log SMART Write Log SMART Enable Operations SMART Disable Operations SMART Return Status SMART Enable/Disable Automatic Off-line...
  • Page 122 Retry. Original meaning is obsoleted, there is no difference between 0 and 1. (Use of 0 is recommended for future compatibility.). Option Bit. Indicates that the Option Bit of the Sector Count Register should be specified. (This bit is used by Set Max Address command) Valid.

  • Page 123: Check Power Mode (E5H/98H)

    11.1 Check Power Mode (E5h/98h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 124: Device Configuration Overlay (B1H)

    11.2 Device Configuration Overlay (B1h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 125: Device Configuration Freeze Lock (Subcommand C1H)

    11.2.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h) The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings. After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command, all DEVICE CONFIGURATION SET, DEVICE CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, and DEVICE CONFIGURATION RESTORE commands are aborted by the device.

  • Page 126: Figure 93. Device Configuration Overlay Data Structure

    Multiword DMA modes supported 15-3 Reserved 1 = Multiword DMA mode 2 and below are supported 1 = Multiword DMA mode 1 and below are supported 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported 15-6 Reserved 1 = Ultra DMA mode 5 and below are supported 1 = Ultra DMA mode 4 and below are supported 1 = Ultra DMA mode 3 and below are supported...

  • Page 127: Figure 94. Dco Error Information Definition

    Cylinder high Invalid word location Cylinder low Invalid bit location (bits (7:0)) Sector Number Invalid bit location (bits 15:8)) Sector count Error reason code & description DCO feature is frozen Device is now Security Locked mode Device feature is already modified with DCO User attempt to disable any feature enabled Device is now SET MAX Locked or Frozen mode Protected area is now established...

  • Page 128: Execute Device Diagnostic (90H)

    11.3 Execute Device Diagnostic (90h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 129: Flush Cache (E7H)

    11.4 Flush Cache (E7h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 130: Flush Cache Ext (Eah)

    11.5 Flush Cache Ext (EAh) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...

  • Page 131: Format Track (50H)

    11.6 Format Track (50h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 132 Input parameters from the device In LBA mode this register specifies current LBA address bits 0-7. (L=1) Sector Number In LBA mode this register specifies current LBA address bits 8-15 (Low), Cylinder High/Low 16-23 (High). In LBA mode this register specifies current LBA address bits 24-27. (L=1) The Error Register.

  • Page 133: Format Unit (F7H)

    11.7 Format Unit (F7h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 134: Identify Device (Ech)

    11.8 Identify Device (ECh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 135: Figure 101. Identify Device Information (Part 1 Of 6)

    The Identify Device command requests the device to transfer configuration information to the host. The device will transfer a sector to the host containing the information described in the figure below. Note: * in the Content field indicates vendor specific use of those parameters. Word Content Description...

  • Page 136: Figure 102. Identify Device Information (Part 2 Of 6)

    Word Content Description 4000H Capabilities, bit assignments: 15-14(=01) Word 50 is valid 13– 1(=0) Reserved Minimum value of Standby timer (=0) less than 5 minutes (=1) equal to or greater than 5 minutes 0200H PIO data transfer cycle timing mode 0200H DMA data transfer cycle timing mode.

  • Page 137: Figure 103. Identify Device Information (Part 3 Of 6)

    Word Content Description 69-74 0000H Reserved 00XXH Queue depth 15- 5 Reserved 4- 0 Maximum queue depth 76-79 0000H Reserved 007CH Major version number 15- 0 (=7C)ATA-2, ATA-3, ATA/ATAPI-4, ATA/ATAPI-5, and ATA/ATAPI-6 0019H Minor version number 15- 0 (=19)ATA/ATAPI-6 T13 1410D revision 3a 74EBH Command set supported 15(=0)

  • Page 138: Figure 104. Identify Device Information (Part 4 Of 6)

    Word Content Description 4023H Command set/feature supported extension 15-14 Word 84 is valid 13- 6 Reserved (=1) General Purpose Logging feature set supported 4- 2 Reserved (=1) SMART self-test supported (=1) SMART error logging supported XXXXH Command set/feature enabled Reserved NOP command READ BUFFER command WRITE BUFFER command...

  • Page 139: Figure 105. Identify Device Information (Part 5 Of 6)

    Word Content Description 0X3FH Ultra DMA transfer modes 15- 8 (=xx) Current active Ultra DMA transfer mode 15-14 Reserved (=0) Mode 5 1= Active 0= Not Active Mode 4 1= Active 0= Not Active Mode 3 1= Active 0= Not Active Mode 2 1= Active 0= Not Active...

  • Page 140: Figure 106. Identify Device Information (Part 6 Of 6)

    Word Content Description 95-99 0000H Reserved 100-103 xxxxH Minimum user LBA address for 48-bit Address feature 104-126 0000H Reserved 0000H Removable Media Status Notification feature set 0000H = Not supported XXXXH Security status. Bit assignments 15- 9 Reserved Security Level 1= Maximum, 0= High 7- 6 Reserved...

  • Page 141: Idle (E3H/97H)

    11.9 Idle (E3h/97h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error - - - - - - - -...

  • Page 142: Idle Immediate (E1H/95H)

    11.10 Idle Immediate (E1h/95h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 143: Initialize Device Parameters (91H)

    11.11 Initialize Device Parameters (91h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 144: Nop (00H)

    11.12 NOP (00h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error V V V V V V V V...

  • Page 145: Read Buffer (E4H)

    11.13 Read Buffer (E4h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 146: Read Dma (C8H/C9H)

    11.14 Read DMA (C8h/C9h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 147 The retry bit. This bit is ignored. Input parameters from the device The number of requested sectors not transferred. This will be zero unless an Sector Count unrecoverable error occurs. The sector number of the last transferred sector. (L=0) Sector Number In LBA mode this register contains current LBA bits 0 - 7.

  • Page 148: Read Dma Ext (25H)

    11.15 Read DMA Ext (25h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 149 Output Parameters To The Device The number of sectors to be transferred low order, bits (7:0). Sector Count Current The number of sectors to be transferred high order, bits (15:8). If Sector Count Previous 0000h in the Sector Count register is specified, then 65,536 sectors will be transferred.

  • Page 150: Read Dma Queued (C7H)

    11.16 Read DMA Queued (C7h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 151 Input parameters from the device on bus release Bits 7 - 3 (Tag) contain the Tag of the command being bus released. Sector Count Bit 2 (REL) is set to one. Bit 1 (I/O) is cleared to zero. Bit 0 (C/D) is cleared to zero. Sector Number, Cylinder High/low, H n/a.

  • Page 152: Read Dma Queued Ext (26H)

    11.17 Read DMA Queued Ext (26h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 153 Output Parameters To The Device Number of sectors to be transferred low order, bits (7:0). Feature Current Number of sectors to be transferred high order, bits (15:8). 0000h in Feature Previous the Feature register indicates that 65,536 sectors are to be transferred. Bits (7:3) (Tag) contain the Tag for the command being delivered.

  • Page 154: Read Log Ext (2Fh)

    11.18 Read Log Ext (2Fh) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...

  • Page 155: General Purpose Log Directory

    Content Feature set Type address Log directory Read Only Extended Comprehensive SMART error SMART error Read Only logging SMART self-test log SMART self-test See Note Extended SMART self-test log SMART self-test Read Only 80h-9Fh Host vendor specific SMART Read/Write Figure 117. Log Address Definition Note: If log address 06h is accessed using the Read Log Ext or Write Log Ext commands, command abort shall be returned.

  • Page 156: Extended Comprehensive Smart Error Log

    11.18.2 Extended Comprehensive SMART Error log The figure below defines the format of each of the sectors that comprise the Extended Comprehensive SMART error log. Error log data structure shall not include errors attributed to the receipt of faulty com- mands such as command codes not implemented by the device or requests with invalid parameters or in valid addresses.

  • Page 157: Figure 70. Device Control Register

    Data format of each error log structure is shown in the figure below. Description Bytes Offset 1st command data structure 2nd command data structure 3rd command data structure 4th command data structure 5th command data structure Error data structure Figure 120. Extended Error log data structure Command data structure: Data format of each command data structure is shown below.
  • Page 158 Error data structure: Data format of error data structure is shown below. Description Bytes Offset Reserved Error register Sector count register (7:0) (see Note) Sector count register (15:8) (see Note) Sector number register (7:0) Sector number register (15:8) Cylinder Low register (7:0) Cylinder Low register (15:8) Cylinder High register (7:0) Cylinder High register (15:8)

  • Page 159: Extended Self-Test Log Sector

    11.18.3 Extended Self-test log sector The figure below defines the format of each of the sectors that comprise the Extended SMART self-test log. The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit entries contained in the SMART self-test log, defined in 11.42.6, "Self-test log data structure" on page0 203, shall also be included in the Extended SMART self-test log with all 48-bit entries.

  • Page 160: Figure 124. Extended Self-Test Log Descriptor Entry

    11.18.3.3 Extended Self-test log descriptor entry The content of the self-test descriptor entry is shown below. Description Bytes Offset Self-test number Self-test execution status Power-on life timestamp in hours Self-test failure check point Failing LBA (7:0) Failing LBA (15:8) Failing LBA (23:16) Failing LBA (31:24) Failing LBA (39:32) Failing LBA (47:40)

  • Page 161: Read Long (22H/23H)

    11.19 Read Long (22h/23h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 162 Input parameters from the device The number of requested sectors not transferred. Sector Count The sector number of the transferred sector. (L=0) Sector Number In LBA mode this register contains current LBA bits 0 - 7. (L=1) The cylinder number of the transferred sector. (L=0) Cylinder High/Low In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High).

  • Page 163: Read Multiple (C4H)

    11.20 Read Multiple (C4h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 164 In LBA mode this register contains current LBA bits 0 - 7. (L=1) The cylinder number of the last transferred sector. (L=0) Cylinder High/Low In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) The head number of the last transferred sector.

  • Page 165: Read Multiple Ext (29H)

    11.21 Read Multiple Ext (29h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 166 Output Parameters To The Device The number of continuous sectors to be transferred low order, bits Sector Count Current (7:0). The number of continuous sectors to be transferred high order, bits Sector Count Previous (15:8). If 0000h is specified in the Sector Count register, then 65,536 sectors will be transferred.

  • Page 167: Read Native Max Address (F8H)

    11.22 Read Native Max Address (F8h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 168: Read Native Max Address Ext (27H)

    11.23 Read Native Max Address Ext (27h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...

  • Page 169: Read Sector(S) (20H/21H)

    11.24 Read Sector(s) (20h/21h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 170 Input parameters from the device The number of requested sectors not transferred. This will be zero unless an Sector Count unrecoverable error occurs. The sector number of the last transferred sector. (L=0) Sector Number In LBA mode this register contains current LBA bits 0 - 7. (L=1) The cylinder number of the last transferred sector.

  • Page 171: Read Sector(S) Ext (24H)

    11.25 Read Sector(s) Ext (24h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 172 Output Parameters To The Device The number of continuous sectors to be transferred low order, bits (7:0) Sector Count Current The number of continuous sectors to be transferred high order, bits Sector Count Previous (15:8). If zero is specified in the Sector Count register, then 65,536 sectors will be transferred.

  • Page 173: Read Verify Sector(S) (40H/41H)

    11.26 Read Verify Sector(s) (40h/41h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 174 The sector number of the last transferred sector. (L=0) Sector Number In LBA mode this register contains current LBA bits 0 - 7. (L=1) The cylinder number of the last transferred sector. (L=0) Cylinder High/Low In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) The head number of the last transferred sector.

  • Page 175: Read Verify Sector(S) Ext (42H)

    11.27 Read Verify Sector(s) Ext (42h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 176 Output Parameters To The Device The number of continuous sectors to be verified low order, bits (7:0). Sector Count Current The number of continuous sectors to be verified high order, bits (15:8). Sector Count Previous If zero is specified in the Sector Count register, then 65,536 sectors will be verified.

  • Page 177: Recalibrate (1Xh)

    11.28 Recalibrate (1xh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error - - - - - - - -...

  • Page 178: Security Disable Password (F6H)

    11.29 Security Disable Password (F6h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 179: Security Erase Prepare (F3H)

    11.30 Security Erase Prepare (F3h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 180: Security Erase Unit (F4H)

    11.31 Security Erase Unit (F4h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 181 Zero indicates that the device should check the supplied password against the Identifier user password stored internally. One indicates that the device should check the given password against the master password stored internally. The Security Erase Unit command erases all user data and disables the security mode feature (device lock function).

  • Page 182: Security Freeze Lock (F5H)

    11.32 Security Freeze Lock (F5h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 183: Security Set Password (F1H)

    11.33 Security Set Password (F1h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 184: Figure 142. Security Set Password Information

    Word Description Control Word bit 0 : Identifier (1-Master, 0-User) bit 1-7 : Reserved bit 8 : Security level (1-Maximum, 0-High) bit 9-15 : Reserved 01-16 Password (32 bytes) Master Password Revision Code Valid if Word 0 bit 0 = 1 18-255 Reserved Figure 142.

  • Page 185: Security Unlock (F2H)

    11.34 Security Unlock (F2h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 186: Figure 144. Security Unlock Information

    Word Description Control Word bit 0 : Identifier (1-Master, 0-User) bit 1-15 : Reserved 01-16 Password (32 bytes) 17-255 Reserved Figure 144. Security Unlock Information Zero indicates that device regards Password as User Password. One indicates Identifier that device regards Password as Master Password. The user can detect if the attempt to unlock the device has failed due to a mismatched password as this is the only reason that an abort error will be returned by the drive AFTER the password information has been sent to the device.

  • Page 187: Seek (7Xh)

    11.35 Seek (7xh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error - - - - - - - -...

  • Page 188: Service (A2H)

    11.36 Service (A2h) Command Block Output Registers Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Feature - - - - - - - - Sector Count - - - - - - - - Sector Number - - - - - - - - Cylinder Low...

  • Page 189: Set Features (Efh)

    11.37 Set Features (EFh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 190: Set Transfer Mode

    Disable Advanced Power Management Disable Power-up in Standby mode Disable Address Offset mode Enable read look-ahead feature 4 bytes of ECC apply on Read Long/Write Long commands Disable Automatic Acoustic Management Enable reverting to power on defaults Disable release interrupt Note: After a power on reset of hard reset the device is set to the following features as default: Write cache : Enable...

  • Page 191: Automatic Acoustic Management

    The idle time to Low power idle mode and Low RPM standby mode vary according to the value in Sector Count register as follows: When Low power idle mode is the deepest Power Saving mode, = (x − 80h) & 5 + 120 sec (120 [ y [ 435) =N/A (the device does not go to Low RPM standby mode) When Low RPM standby mode is the deepest Power Saving mode and the value in Sector Count...
  • Page 192 The device preserves enabling or disabling of Automatic Acoustic Management and the current Automatic Acoustic Management level setting across all forms of reset, that is, Power on, Hardware, and Software Resets. Deskstar 180GXP hard disk drive specifications...

  • Page 193: Set Max Address (F9H)

    11.38 Set Max Address (F9h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 194 After a successful command completion, Identify Device response words (61:60) shall reflect the maxi- mum address set with this command. If the 48-bit Address feature set is supported, the value placed in Identify Device response words (103:100) shall be the same as the value placed in words (61:60). However, if the device contains greater than 268,435,455 sectors, the capacity addressable with 28-bit commands, and the address requested is 268,435,455, the max address shall be changed to the native maximum address, the value placed in words (61:60) shall be 268,435,455 and the value placed in words (103:100) shall be the native maximum...

  • Page 195: Set Max Set Password (Feature = 01H)

    11.38.1 Set Max Set Password (Feature = 01h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 196: Set Max Lock (Feature = 02H)

    11.38.2 Set Max Lock (Feature = 02h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...

  • Page 197: Set Max Unlock (Feature = 03H)

    11.38.3 Set Max Unlock (Feature = 03h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 198: Set Max Freeze Lock (Feature = 04H)

    11.38.4 Set Max Freeze Lock (Feature = 04h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 199: Set Max Address Ext (37H)

    11.39 Set Max Address Ext (37h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 200 If the device in Address Offset mode receives this command with the nonvolatile option, the device returns aborted error to the host. The device returns the command aborted for a second non-volatile Set Max Address Ext command until next power on or hardware reset. Output Parameters To The Device Option bit for selection whether nonvolatile or volatile.

  • Page 201: Set Multiple (C6H)

    11.40 Set Multiple (C6h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 202: Sleep (E6H/99H)

    11.41 Sleep (E6h/99h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error - - - - - - - -...

  • Page 203: Function Set (B0H)

    11.42 S.M.A.R.T. Function Set (B0h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 204: Subcommand

    11.42.1 S.M.A.R.T. Subcommand In order to select a subcommand the host must write the subcommand code to the Features Register of the device before issuing the S.M.A.R.T. Function Set command. The subcommands and their respective codes are listed below. Code Subcommand SMART Read Attribute Values SMART Read Attribute Thresholds...
  • Page 205 Upon receipt of the subcommand from the host the device asserts BSY, enables or disables the Autosave feature, clears BSY, and asserts INTRQ. 11.42.1.4 SMART Save Attribute Values (Subcommand D3h) This subcommand causes the device to immediately save any updated Attribute Values to the Attribute Data sector of the device regardless of the state of the Attribute Autosave feature.

  • Page 206: Figure 158. Log Sector Addresses

    11.42.1.6 SMART Read Log Sector (Subcommand D5h) This command returns the specified log sector contents to the host. The 512 bytes data are returned at a command and the Sector Count value shall be set to one. The Sector Number shall be set to specify the log sector address. Log sector address Content Type...
  • Page 207 Operations command will be preserved in the Attribute Data Sectors of the device. If the device is re-enabled, these Attribute Values will be updated as needed upon receipt of a SMART Read Attribute Values or SMART Save Attribute Values command. 11.42.1.10 SMART Return Status (Subcommand DAh) This command is used to communicate the reliability status of the device upon the request of the host.

  • Page 208: Device Attributes Data Structure

    11.42.2 Device Attributes Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the SMART Read Attribute Values subcommand. All multibyte fields shown in these data structures are in byte ordering, that is, the least significant byte occupies the lowest numbered byte address location in the field.

  • Page 209: Figure 160. Individual Attribute Data Structure

    11.42.2.2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure. Description Byte Offset Attribute ID Number (01h to FFh) Status flags Attribute Value (valid values from 01h to FDh) Vendor Specific Total Bytes Figure 160.
  • Page 210 Status Flag definitions Definition Pre-failure/advisory bit An attribute value less than or equal to its corresponding attribute threshold indicates an advisory condition where the usage or age of the device has exceeded its intended design life period. An attribute value less than or equal to its corresponding attribute threshold indicates a pre-Failure condition where imminent loss of data is being predicted.
  • Page 211 11.42.2.5 Total time in seconds to complete off-line data collection activity This field tells the host how many seconds the device requires to complete the off-line data collection activity. 11.42.2.6 Off-line data collection capability Definition Execute Off-line Immediate implemented bit SMART Execute Off-line Immediate subcommand is not implemented SMART Execute Off-line Immediate subcommand is implemented Enable/disable Automatic Off-line implemented bit...

  • Page 212: Device Attribute Thresholds Data Structure

    The Data Structure Checksum is the two's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data structure. 11.42.3 Device Attribute Thresholds Data Structure The following defines the 512 bytes that make up the Attribute Threshold information. This data structure is accessed by the host in its entirety using the SMART Read Attribute Thresholds.

  • Page 213: Smart Log Directory

    11.42.3.5 Data Structure Checksum The Data Structure Checksum is the two's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data structure. 11.42.4 SMART Log Directory The figure below defines the 512 bytes that make up the SMART Log Directory. The SMART Log Directory is SMART Log Address zero and is defined as one sector long.

  • Page 214: Smart Summary Error Log Sector

    11.42.5 SMART summary error log sector The following figure defines the 512 bytes that make up the SMART summary error log sector. All multi- byte fields shown in this data structure follow the ATA/ATAPI-6 specifications for byte ordering. Description Byte Offset SMART error log version Error log index...

  • Page 215: Figure 165. Error Log Data Structure

    11.42.5.4 Error log data structure Data format of error data structure is shown below. Description Byte Offset 1st command data structure 2nd command data structure 3rd command data structure 4th command data structure 5th command data structure Error data structure Figure 165.

  • Page 216: Figure 167. Error Data Structure

    Error data structure: Data format of error data structure is shown below. Description Byte Offset Reserved Error register Sector count register Sector number register Cylinder Low register Cylinder High register Device/Head register Status register Extended error data (vendor specific) State Life time stamp (hours) Figure 167.

  • Page 217: Self-Test Log Data Structure

    11.42.6 Self-test log data structure The following figure defines the 512 bytes that make up the Self-test log sector. All multibyte fields shown in these data structures follow the ATA/ATAPI-5 specifications for byte ordering. Description Byte Offset Data structure revision Self-test number n*18h+02h Self-test execution status...

  • Page 218: Error Reporting

    11.42.7 Error reporting The following table shows the values returned in the Status and Error Registers when specific error con- ditions are encountered by a device. Status Error Error condition Register Register A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being loaded into the Cylinder High and Cylinder Low registers.

  • Page 219: Standby (E2H/96H)

    11.43 Standby (E2h/96h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error - - - - - - - -...
  • Page 220 Output Parameters To The Drive Time-out Parameter. If it is 0, the time-out interval (Standby Timer) is NOT Sector Count disabled. If it is nonzero, the automatic power down sequence is enabled. The time-out interval is shown below: Value Time-out Timer disabled 1-240 Value x 5 seconds...

  • Page 221: Standby Immediate (E0H/94H)

    11.44 Standby Immediate (E0h/94h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...

  • Page 222: Write Buffer (E8H)

    11.45 Write Buffer (E8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data - - - - - - - -...

  • Page 223: Write Dma (Cah/Cbh)

    11.46 Write DMA (CAh/CBh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data - - - - - - - -...
  • Page 224 Input parameters from the device The number of requested sectors not transferred. This will be zero unless an Sector Count unrecoverable error occurs. The sector number of the last transferred sector. (L=0) Sector Number In LBA mode this register contains current LBA bits 0 - 7. (L=1) The cylinder number of the last transferred sector.

  • Page 225: Write Dma Ext (35H)

    11.47 Write DMA Ext (35h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 226 Output Parameters To The Device The number of continuous sectors to be transferred low order, bits Sector Count Current (7:0). The number of continuous sectors to be transferred high order bits Sector Count Previous (15:8). If zero is specified in the Sector Count register, then 65,536 sectors will be transferred.

  • Page 227: Write Dma Queued (Cah/Cbh)

    11.48 Write DMA Queued (CAh/CBh) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 228 Input parameters from the device on bus release Bits 7 - 3 (Tag) contain the Tag of the command being bus released. Sector Count Bit 2 (REL) is set to one. Bit 1 (I/O) is cleared to zero. Bit 0 (C/D) is cleared to zero. Sector Number, Cylinder High/Low, H n/a.

  • Page 229: Write Dma Queued Ext (36H)

    11.49 Write DMA Queued Ext (36h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 230 Output Parameters To The Device number of sectors to be transferred low order, bits (7:0). Feature Current number of sectors to be transferred high order, bits (15:8). A value of 0000h in the Feature register indicates that 65,536 sectors are to be Feature Previous transferred.

  • Page 231: Write Log Ext (3Fh)

    11.50 Write Log Ext (3Fh) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 232 Output Parameters To The Device Sector Count Current The number of sectors to be written to the specified log low order, bits (7:0). Sector Count Previous The number of sectors to be written to the specified log high orders, bits (15:8). If the number of sectors is greater than the number indicated in the Log directory, which is available in Log number zero, the device shall return command aborted.

  • Page 233: Write Long (32H/33H)

    11.51 Write Long (32h/33h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 234 Input parameters from the device The number of requested sectors not transferred. Sector Count The sector number of the sector to be transferred. (L=0) Sector Number In LBA mode this register contains current LBA bits 0 - 7. (L=1) The cylinder number of the sector to be transferred. (L=0) Cylinder High/Low In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High).

  • Page 235: Write Multiple (C5H)

    11.52 Write Multiple (C5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - Data Data - - - - - - - -...
  • Page 236 The sector number of the last transferred sector. (L=0) Sector Number In LBA mode this register contains current 1.5 LBA bits 0 - 7. (L=1) The cylinder number of the last transferred sector. (L=0) Cylinder High/Low In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) The head number of the last transferred sector.

  • Page 237: Write Multiple Ext (39H)

    11.53 Write Multiple Ext (39h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 238 Output Parameters To The Device The number of continuous sectors to be transferred low order, bits (7:0) Sector Count Current The number of continuous sectors to be transferred high order, bits Sector Count Previous (15:8). If zero is specified in the Sector Count register, then 65,536 sectors shall be transferred.

  • Page 239: Write Sector(S) (30H/31H)

    11.54 Write Sector(s) (30h/31h) Command Block Output Command Block Input Registers Registers Register Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Data - - - - - - - - - - - - - - - - Feature Error...
  • Page 240 The sector number of the last transferred sector. (L=0) Sector Number In LBA mode this register contains current LBA bits 0 - 7. (L=1) The cylinder number of the last transferred sector. (L=0) Cylinder High/Low In LBA mode this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1) The head number of the last transferred sector.

  • Page 241: Write Sector(S) Ext (34H)

    11.55 Write Sector(s) Ext (34h) Command Block Output Command Block Input Registers Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
  • Page 242 Output Parameters To The Device The number of continuous sectors to be transferred low order, bits Sector Count Current (7:0). The number of continuous sectors to be transferred high order bits Sector Count Previous (15:8). If zero is specified, then 65,536 sectors will be transferred. LBA (7:0).

  • Page 243: Timings

    12.0 Timings The timing of BSY and DRQ in Status Register is shown in the figure below. Function Interval Start Stop Time-out Power On Device Busy After Status Register Power On 400 ns Power On BSY=1 Device Ready Status Register Power On 31 sec After Power On...
  • Page 244 This page intentionally left blank.

  • Page 245: Index

    Index Abbreviations used, 1 Flammability, 59 Acoustics, 57 Formatted Capacity, 9 Actuator, 7 Full stroke seek, 13 Address Offset, 91 Addressing of registers, 38 Advanced Power Management, 90 General features, 3 AT signal connector, 21 German Safety Mark, 59 Automatic Acoustic Management, 91 Average latency, 14 Head disk assembly, 7 Head switch time, 13...
  • Page 246 Seek Overlap, 88 Shipped format, 19 Passwords, 80 Shipping conditions, 45 Performance characteristics, 12 Shock, 55 PIO Data In commands, 96 Signal definition, 22 PIO Data Out commands, 98 Signal timings, 26 PIO timings, 27 Simple sequential access, 16 PList physical format, 19 Single track seek time, 14 Power management, 76 Sound power levels, 57...
  • Page 247 States, other countries, or both. Other product names are trademarks or registered trademarks of their respective companies. References in this publication to Hitachi Global Storage Technologies products, programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates.

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