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4.9 PT6315(IC801):FL Display driverBlock diagram
• Block diagram
DIN
DOUT
Serial
Data
CLK
Interface
STB
R
OSC
OSC
LED1
LED2
LED
Driver
LED3
LED4
• Pin function
Pin No.
Symbol
1 to 4
LED1 to LED4
5
OSC
6
DOUT
7
DIN (Schmitt Trigger)
8
CLK (Schmitt Trigger)
9
STB (Schmitt Trigger)
10,11
K1 to K2
12,44
VSS
13,43
VDD
14 to 29
SG1/KS1 to SG16/KS16
30
VEE
31 to 38 SG17/GR12 to SG24/GR5
39 to 42
GR4 to GR1
Control
Display Memory
(24bits x 12 Words)
Timing Generator
Key Matrix
Memory
K1
K2
VDD GND
I/O
O
LED Output Pin
I
Oscillator Input Pin
A resistor is connected to this pin to determine the oscillation frequency
O
Data Output Pin(N-Channel, Open-Drain)
This pin outputs serial data at the falling edge of the shift clock(starting from the lower
bit)
I
Data Output Pin
This pin inputs serial data at the rising edge of the shift clock(starting from the lower bit)
I
Clock Input Pin
This pin reads serial data at the rising edge and outputs data at the falling edge.
I
Serial Interface Strobe Pin
The data input after the STB has fallen is processed as a command.
When this pin is "HIGH",CLK is ignored.
I
Key Data Input Pins
The data inputted to these pins are latched at the end of the display cycle.
-
Logic Ground Pin
-
Logic Power Supply
O
High-Voltage Segment Output Pins
Also acts as the Key Source
-
Pull-Down Level
O
High Voltage Segment/Grid Output Pins
O
High Voltage Grid Output Pins
Segment
Driver/
Grid
Driver/
Key Scan
Output
Grid
Driver/
Dimming Circuit
VEE
Description
XV-N50BK,XV-N55SL
SG1/KS1
SG16/KS16
SG17/GR12
SG24/GR5
GR1
GR4
(No.A0041)1-37
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