JVC XV-N50BK Service Manual page 31

4.6 K4S643232E-TC60(IC505):DRAM
• Block diagram
CLK
ADD
LCKE
LRAS
CLK
• Pin function
Symbol Description
CLK System clock signal input
CS Chip select input
CKE Clock enable
A0~A10 Address
BA0,1 Bank select address
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQM0~3 Data input/output mask
DQ0~31 Data input/output
VDD Power supply terminal
VSS Connect to ground
VDDQ Power supply terminal
VSSQ Connect to ground
NC Non connect
Bank select
LCBR LWE
LCAS
Timing register
CKE CS RAS
Data input register
512K x 32
512K x 32
512K x 32
512K x 32
Column decoder
Latency & burst length
Programming register
LWCBR
CAS WE DQM
XV-N50BK,XV-N55SL
LWE
LDQM
DQI
LDQM
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