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XV-N50BK,XV-N55SL
4.7 SST39VF160-9CEK (IC509) : 16M EEPROM
• Pin layout
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
/WE
/RST
NC
NC
R/B
A18
A17
A7
A6
A5
A4
A3
A2
A1
• Block diagram
A19~A0
• Pin function
Symbol
A19~A0
Address Inputs
DQ15~DQ0
Data Input/Output
/CE
Chip Enable
/OE
Output Enable
/WE
Write Enable
VCC
Power Supply
Vss
Ground
NC
No Connection
1-32 (No.A0041)
1
48
A16
2
47
/BYTE
3
46
Vss
4
45
D15
5
44
D7
6
43
D14
7
42
D6
8
41
D13
9
40
D5
10
39
D12
11
38
D4
12
37
VCC
13
36
D11
14
35
D3
15
34
D10
16
33
D2
17
32
D9
18
31
D1
19
30
D8
20
29
D0
21
28
/OE
22
27
Vss
23
26
/CE
24
25
A0
Address Buffer & Latches
/CE
Control Logic
/OE
/WE
Pin name
To provide memory addresses. During sector erase A19~A11 address lines will select the
sector. During block erase A19~A15 address lines will select the block.
To output data during read cycles and receive input data during write cycles. Data is inter-
nally latched during a write cycle. The outputs are in tri-state when /OE or /CE is high.
To activate the device when /CE is low.
To gate the data output buffers.
To control the write operations.
To provide 3-volt supply ( 2.7V-3.6V ).
Connect to ground
X-Decoder
I/O Buffers & Data Latches
Function
16,777,216Bit
EEPROM
Cell Array
Y-Decoder
DQ15~DQ0
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