Dram (Dimm) Sockets; System Bios; L2 Cache Subsystem; Cacheable And Non-Cacheable Regions - BCM Advanced Research IN440EX User Manual

DRAM (DIMM) Sockets

Connection to the main system DRAM can be done via two (2) DIMM connectors on
the system PWA.
Reference:
Connector Type:
Connector Part Number:

System BIOS

The system and video BIOS are stored in a 2M-bit (256Kx8) Flash Memory device. The
system BIOS is always shadowed and cached.

L2 Cache Subsystem

The Pentium® II processor cartridge provides an unified 0KB or 512KB second level (L2)
cache to complement the level one data and instruction (L1) internal caches. The L2 cache
is Direct-Mapped non-sectored, supporting the Write Back policy architecture.
Table 2.4. L2 Cache latency with Burst SRAM
Cycle Type
Burst Read
Burst Write (Write-back)
Single Read
Single Write
Pipelined Back-to-Back Burst Reads
1
: The back-to-back cycles do not account for CPU idle clocks between cycles

Cacheable and Non-Cacheable Regions

The system caches the following regions:
All system memory, including 0 to 640 KB and all memory present above 1
•
MB up to 1GB.
System and integrated video controller BIOS.
•
The system does not cache the following regions:
• The video memory block from A0000 to BFFFF.
BCM Advanced Research
DIMM0, DIMM1
female, 168 pin DIMM, in-line connector
Berg. 91145-60024 (Or equivalent)
Clock Count
X-1-1-1
X-1-1-1
X
X
1
X-1-1-1,1-1-1-1
35