Fujitsu MHU2100AT Product Manual page 94

Interface
5.3.2 Command descriptions
The contents of the I/O registers to be necessary for issuing a command and the
example indication of the I/O registers at command completion are shown as
following in this subsection.
Example: READ SECTOR(S)
At command issuance (I/O registers setting contents)
Bit
1F7 (CM)
H
1F6 (DH)
H
1F5 (CH)
H
1F4 (CL)
H
1F3 (SN)
H
1F2 (SC)
H
1F1 (FR)
H
At command completion (I/O registers contents to be read)
Bit
1F7 (ST)
H
1F6 (DH)
H
1F5 (CH)
H
1F4 (CL)
H
1F3 (SN)
H
1F2 (SC)
H
1F1 (ER)
H
CM: Command register
DH: Device/Head register
CH: Cylinder High register
CL: Cylinder Low register
SN: Sector Number register
5-18
7 6 5 4
0 0 1 0
x L x DV
Start cylinder address [MSB] / LBA
Start cylinder address [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
7 6 5 4
Status information
x L x DV
End cylinder address [MSB] / LBA
End cylinder address [LSB] / LBA
End sector No. / LBA [LSB]
X'00'
Error information
FR: Features register
ST: Status register
ER: Error register
L: LBA (logical block address) setting bit
DV: Device address. bit
3 2 1 0
0 0 0 0
Head No. / LBA [MSB]
3 2 1 0
Head No. / LBA [MSB]
C141-E202-01EN