Page 1 C141-E192-01EN MHT2080AT, MHT2060AT, MHT2040AT MHT2030AT, MHT2020AT DISK DRIVES PRODUCT MANUAL...
Page 2 “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
Page 3: Revision History
Revision History (1/1) Revised section (*1) Edition Date Details (Added/Deleted/Altered) 2003-01-20 *1 Section(s) with asterisk (*) refer to the previous edition when those were deleted. C141-E192-01EN...
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Page 5 This manual describes the MHT Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.
Page 6: Operating Environment
Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: In the text, the alert signal is centered, followed below by the indented message.
Page 7 “Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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Page 9: Important Alert Items
Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occur if the user does not perform the procedure correctly.
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Page 11: Manual Organization
Manual Organization MHT2080AT, MHT2060AT, MHT2040AT MHT2030AT, MHT2020AT DISK DRIVES PRODUCT MANUAL (C141-E192) <This manual> MHT2080AT, MHT2060AT, MHT2040AT MHT2030AT, MHT2020AT DISK DRIVES MAINTENANCE MANUAL (C141-F063) C141-E192-01EN • Device Overview • Device Configuration • Installation Conditions • Theory of Device Operation • Interface •...
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Page 13: Table Of Contents
Device Overview ... 1-1 Features... 1-2 1.1.1 Functions and performance... 1-2 1.1.2 Adaptability ... 1-2 1.1.3 Interface ... 1-3 Device Specifications ... 1-4 1.2.1 Specifications summary... 1-4 1.2.2 Model and product number... 1-5 Power Requirements ... 1-5 Environmental Specifications ... 1-8 Acoustic Noise...
Page 14 Contents CHAPTER 3 Installation Conditions... 3-1 Dimensions...3-2 Mounting...3-3 Cable Connections ...3-9 3.3.1 Device connector...3-9 3.3.2 Cable connector specifications ...3-10 3.3.3 Device connection...3-10 3.3.4 Power supply connector (CN1)...3-11 Jumper Settings ...3-11 3.4.1 Location of setting jumpers ...3-11 3.4.2 Factory default setting...3-12 3.4.3 Master drive-slave drive setting...3-12 3.4.4...
Page 15 4.6.2 Write circuit ... 4-9 4.6.3 Read circuit ... 4-11 4.6.4 Digital PLL circuit ... 4-12 Servo Control ... 4-13 4.7.1 Servo control circuit ... 4-13 4.7.2 Data-surface servo format... 4-16 4.7.3 Servo frame format ... 4-18 4.7.4 Actuator motor control ... 4-19 4.7.5 Spindle motor control ...
Page 16 Contents 5.5.3.1 Initiating an Ultra DMA data in burst...5-119 5.5.3.2 The data in transfer ...5-120 5.5.3.3 Pausing an Ultra DMA data in burst...5-120 5.5.3.4 Terminating an Ultra DMA data in burst...5-121 5.5.4 Ultra DMA data out commands ...5-124 5.5.4.1 Initiating an Ultra DMA data out burst...5-124 5.5.4.2 The data out transfer ...5-124 5.5.4.3 Pausing an Ultra DMA data out burst...5-125 5.5.4.4 Terminating an Ultra DMA data out burst...5-126...
Page 17 Contents Glossary...GL-1 Acronyms and Abbreviations ... AB-1 Index ... IN-1...
Page 18 Contents Illustrations Figures...
Page 19 Contents...
Page 20 Contents Tables...
Page 21: Chapter 1 Device Overview
CHAPTER 1 Device Overview Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects 1.10 Load/Unload Function 1.11 Advanced Power Management Overview and features are described in this chapter, and specifications and power requirement are described.
Page 22: Features
RLL recording method and 30 recording zone technology. The MHT Series has a formatted capacity of 80 GB (MHT2080AT), 60 GB (MHT2060AT), 40 GB (MHT2040AT), 30 GB (MHT2030AT) and 20 GB (MHT2020AT) respectively. (3) High-speed Transfer rate The disk drives (the MHT Series) have an internal data rate up to 41.3 MB/s. The disk drive supports an external data rate up to 100 MB/s (U-DMA mode 5).
Page 23: Interface
1.1.3 Interface (1) Connection to ATA interface The MHT-series disk drives have built-in controllers compatible with the ATA interface. (2) 2 MB data buffer The disk drives (the MHT Series) use a 2 MB data buffer to transfer data between the host and the disk media.
Page 24: Device Specifications
Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives (MHT Series). Table 1.1 Specifications (1/2) MHT2080AT MHT2060AT MHT2040AT MHT2030AT MHT2020AT Format Capacity (*1) Number of Sectors (User) 156,301,488 Bytes per Sector Recording Method...
Page 25: Model And Product Number
8.45 GB MHT2040AT 8.45 GB MHT2030AT 8.45 GB MHT2020AT 8.45 GB *1 On using for the units of BIOS parameter. 1.2.2 Model and product number Table 1.2 lists the model names and product numbers of the MHT Series. Table 1.2 Model names and product numbers...
Page 26 Device Overview (3) A negative voltage like the bottom figure isn't to occur at +5 V when power is turned off and, a thing with no ringing. Permissible level: Figure 1.1 Negative voltage at +5 V when power is turned off 0.2 V Time [ms] C141-E192-01EN...
Page 27 50 mA 20 mA — (rank E / MHT2080AT) (rank E / MHT2060AT) (rank E / MHT2040AT) (rank D / MHT2030AT) (rank D / MHT2020AT) 1.3 Power Requirements MHT Series 4.5 W 0.65 W 2.3 W 0.25 W 0.1 W 0.008 W/GB...
Page 28: Environmental Specifications
Device Overview Figure 1.2 Current fluctuation (Typ.) at +5 V when power is turned on (6) Power on/off sequence The voltage detector circuits (the MHT Series) monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence.
Page 29: Acoustic Noise
1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Sound Pressure • Idle mode (DRIVE READY) Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Shock and vibration specification Item Vibration (Swept sine, 1/4 octave per minute)
Page 30: Reliability
Device Overview 1.7 Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h MTBF is defined as follows: Total operation time in all fields MTBF= number of device failure in all fields (*1) *1 “Disk drive defects” refers to defects that involve repair, readjustment, or replacement.
Page 31: Error Rate
1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading data of 10...
Page 32: Advanced Power Management
Device Overview Emergency Unload other than Normal Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Normal Unload cannot be executed. Therefore, the number of Emergency other than Normal Unload is specified.
Page 33 Active Idle: Low power Idle: Standby: APM Mode Mode-0 Mode-1 Mode-2 When the maximum time that the HDD is waiting for commands has been exceeded: Mode-0: Mode shifts from Active condition to Active Idle in 0.2-1.2, and to Low Power Idle in 15 minutes. Mode-1: Mode shifts from Active condition to Active Idle in 0.2-1.2 seconds and to Low power Idle in 10.0-40.0 seconds.
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Page 35: Chapter 2 Device Configuration
CHAPTER 2 Device Configuration Device Configuration System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate. C141-E192-01EN...
Page 36: Device Configuration
Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. Figure 2.1 Disk drive outerview (1) Disk The outer diameter of the disk is 65 mm.
Page 37: System Configuration
44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 5 (100 MB/s). 2.2.2 1 drive connection Figure 2.2 1 drive system configuration C141-E192-01EN 2.2 System Configuration MHT2080AT MHT2060AT MHC2032AT MHT2040AT MHC2040AT MHT2030AT MHT2020AT...
Page 38: Drives Connection
No need to push the top cover of the disk drive. If the over-power worked, the cover could be contacted with the spindle motor. Thus, that could be made it the cause of failure. MHT2080AT MHT2060AT MHC2032AT MHT2040AT (Host adaptor) MHC2040AT MHT2030AT MHT2020AT MHT2080AT MHT2060AT MHC2032AT MHT2040AT MHC2040AT MHT2030AT MHT2020AT IMPORTANT C141-E192-01EN...
Page 39: Chapter 3 Installation Conditions
CHAPTER 3 Installation Conditions Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. For information about handling this hard disk drive and the system installation procedure, refer to the following Integration Guide.
Page 40: Dimensions
Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Figure 3.1 Dimensions C141-E192-01EN...
Page 41: Mounting
3.2 Mounting For information on mounting, see the "FUJITSU 2.5-INCH HDD INTEGRATION GUIDANCE (C141-E144)." (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. (a) Horizontal –1 (c) Vertical –1 (e) Vertical –3 C141-E192-01EN (b) Horizontal –1 (d) Vertical –2 (f) Vertical –4...
Page 42 Installation Conditions (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must be 0.49N·m (5kgf·cm).
Page 43 3.2 Mounting IMPORTANT Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4. For breather hole of Figure 3.4, at least, do not allow its around 2.4 to block.
Page 44 Installation Conditions (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60 C.
Page 45 (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.
Page 46 Installation Conditions General notes Wrist strap Figure 3.7 Handling cautions Installation ·m (5 ·cm). Recommended equipments ESD mat Shock absorbing mat C141-E192-01EN...
Page 47: Cable Connections
3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. Connector, setting pins Figure 3.8 Connector locations C141-E192-01EN 3.3 Cable Connections...
Page 48: Cable Connector Specifications
Installation Conditions 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications ATA interface and power supply cable (44-pin type) For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines.
Page 49: Power Supply Connector (Cn1)
3.3.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). Figure 3.10 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.11 shows the location of the jumpers to select drive configuration and functions.
Page 50: Factory Default Setting
Installation Conditions 3.4.2 Factory default setting Figure 3.12 shows the default setting position at the factory. Figure 3.12 Factory default setting 3.4.3 Master drive-slave drive setting Master drive (disk drive #0) or slave drive (disk drive #1) is selected. Open Open (a) Master drive Figure 3.13 Jumper setting of master or slave drive...
Page 51: Csel Setting
3.4.4 CSEL setting Figure 3.14 shows the cable select (CSEL) setting. Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.15 and 3.16 show examples of cable selection using unique interface cables. By connecting the CSEL of the master drive to the CSEL Line (conducer) of the cable and connecting it to ground further, the CSEL is set to low level.
Page 52: Power Up In Standby Setting
Installation Conditions drive drive Figure 3.16 Example (2) of Cable Select 3.4.5 Power Up in Standby setting When pin C is grounded, the drive does not spin up at power on. 3-14 C141-E192-01EN...
Page 53: Chapter 4 Theory Of Device Operation
CHAPTER 4 Theory of Device Operation Outline Subassemblies Circuit Configuration Power-on Sequence Self-calibration Read/write Circuit Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.
Page 54: Outline
Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).
Page 55: Air Filter
4.2.4 Air filter There are two types of air filters: a breather filter and a circulation filter. The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.
Page 56 Theory of Device Operation (4) Controller circuit Major functions are listed below. Data buffer management ATA interface control and data transfer control Sector format control Defect management ECC control Error recovery and self-diagnosis Figure 4.1 Power Supply Configuration C141-E192-01EN...
Page 57 Data Buffer SDRAM Flash ROM FROM Shock Sensor TLS2255 SP Motor Media Figure 4.2 Circuit Configuration C141-E192-01EN 4.3 Circuit Configuration Console MCU & HDC & RDC Anchor (88i553x; Marvell) Resonator 20MHz Thermistor R/W Pre-Amp HEAD ATA Interface TLS26B624...
Page 58: Power-On Sequence
Theory of Device Operation 4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.
Page 59: Self-Calibration
Power-on Start Self-diagnosis 1 - MPU bus test - Internal register write/read test - Work RAM write/read test The spindle motor starts. Self-diagnosis 2 - Data buffer write/read test Confirming spindle motor speed Load the head assembly Figure 4.3 Power-on operation sequence 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque.
Page 60: Execution Timing Of Self-Calibration
Theory of Device Operation The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control. To compensate torque varying by the cylinder, the disk is divided into 16 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration.
Page 61: Command Processing During Self-Calibration
4.5.3 Command processing during self-calibration This enables the host to execute the command without waiting for a long time, even when the disk drive is performing self-calibration. The command execution wait time is about maximum 72 ms. When the error rate of data reading, writing, or seeking becomes lower than the specified value, self-calibration is performed to maintain disk drive stability.
Page 62 Theory of Device Operation Figure 4.4 Read/write circuit block diagram 4-10 C141-E192-01EN...
Page 63: Read Circuit
4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the ENDEC circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.
Page 64: Digital Pll Circuit
Theory of Device Operation (3) FIR circuit This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) A/D converter circuit This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data.
Page 65: Servo Control
4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.
Page 66 Theory of Device Operation The major internal operations are listed below. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied. b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).
Page 67 (2) Servo burst capture circuit The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. From the servo area on the data area surface, via the data head, the burst signal of SERVO A, SERVO B, SERVO C, and SERVO D is output as shown in Figure 4.9 in subsequent to the servo mark, gray code that indicates the cylinder position, and index information.
Page 68: Data-Surface Servo Format
Theory of Device Operation 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below. (1) Inner guard band This area is located inside the user area, and the rotational speed of the VCM can be controlled on this cylinder area for head moving.
Page 69 CYLn CYLn + 1 W/R Recovery W/R Recovery Servo Mark Servo Mark Gray Code Gray Code Erase Servo A Servo B Erase Servo C Erase Erase Servo D Figure 4.7 Physical sector servo configuration on disk surface C141-E192-01EN Servo frame (150 servo frames per revolution) Data area expand...
Page 70: Servo Frame Format
Theory of Device Operation 4.7.3 Servo frame format As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. The servo frame consists of 6 blocks;...
Page 71: Actuator Motor Control
(1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area generates a timing for demodulating the gray code and position- demodulating the servo A to D by detecting the servo mark. (3) Gray code (including sector address bits) This area is used as cylinder address.
Page 72: Spindle Motor Control
(called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.
Page 73 e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode. (2) Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC.
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Page 75: Chapter 5 Interface
CHAPTER 5 Interface Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA Feature Set Timing This chapter gives details about the interface, and the interface commands and timings. C141-E192-01EN...
Page 76: Physical Interface
Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Host DMACK-: DMA ACKNOWLEDGE DMARQ: DMA REQUEST INTRO: INTERRUPT REQUEST DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS DIOR-:I/O READ HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE:DATA STROBE DURING ULTRA DMA DATA OUT BURST PDIAG-: PASSED DIAGNOSTICS CBLID-: CABLE TYPE IDENTIFIER...
Page 77: Signal Assignment On The Connector
5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal MSTR PUS- (KEY) RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DMARQ DIOW-, STOP DIOR-, HDMRDY, HSTROBE...
Page 78 Interface [signal] [I/O] ENCSEL This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D MSTR- MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting Pin A, B Short: PUS- When pin C is grounded, the drive does not spin up at power on. RESET- Reset signal from the host.
Page 79 [signal] [I/O] CS0- Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers. CS1- Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers. DA 0-2 Binary decoded address signals asserted by the host to access task file registers.
Page 80: Logical Interface
Interface [signal] [I/O] DMARQ This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals.
Page 81: I/O Registers
5.2.1 I/O registers Communication between the host system and the device is done through input- output (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.
Page 82: Command Block Registers
Interface Device/Head, Cylinder High, Cylinder Low, Sector Number registers indicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0, respectively. If the LBA mode is specified with 48-bit address information, the Cylinder High, Cylinder Low, Sector Number registers are set twice.
Page 83 - Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution. - Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not Found error occurred. [Diagnostic code] X’01’: No Error Detected.
Page 84 Interface (5) Sector Number register (X’1F3’) The contents of this register indicates the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command. Under the LBA mode, this register indicates LBA bits 7 to 0.
Page 85 (8) Device/Head register (X’1F6’) The contents of this register indicate the device and the head number. When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines “the number of heads minus 1” (a maximum head No.). Bit 7 Bit 6 - Bit 7: Unused - Bit 6: L.
Page 86 Interface - Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit is 0 while data transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host system should not write the command block registers.
Page 87: Control Block Registers
- Bit 1: Always 0. - Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error. (10) Command register (X’1F7’) The Command register contains a command code being sent to the device.
Page 88: Host Commands
Interface (2) Device Control register (X’3F6’) The Device Control register contains device interrupt and software reset. Bit 7 Bit 6 - Bit 7: High Order Byte (HOB) is the selector bit that selects higher-order information or lower-order information of the EXT system command. If HOB = 1, LBA bits 47 to 24 and the higher-order 8 bits of the sector count are displayed in the task register.
Page 89 Table 5.3 Command code and parameters (1 of 3) Command name READ SECTOR(S) READ MULTIPLE READ DMA READ VERIFY SECTOR(S) WRITE MULTIPLE WRITE DMA WRITE VERIFY WRITE SECTOR(S) RECALIBRATE SEEK INITIALIZE DEVICE PARAMETERS 1 IDENTIFY DEVICE IDENTIFY DEVICE DMA SET FEATURES SET MULTIPLE MODE SET MAX READ NATIVE MAX ADDRESS...
Page 90 Interface Table 5.3 Command code and parameters (2 of 3) Command name IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK FLUSH CACHE DEVICE CONFIGURATION SET MAX ADDRESS SET MAX SET PASSWORD...
Page 91 Table 5.3 Command code and parameters (3 of 3) Command name DEVICE CONFIGURATION IDENTIFY DEVICE CONFIGURATION SET READ NATIVE MAX ADDRESS SET MAX ADDRESS EXT FLUSH CACHE EXT WRITE DMA EXT READ DMA EXT WRITE MULTIPLE EXT READ MULTIPLE EXT WRITE SECTOR (S) EXT READ SECTOR (S) EXT DOWNLOAD MICRO CODE...
Page 92: Command Descriptions
Interface The device parameter is valid, and the head parameter is ignored. Option (customizing) The command is addressed to the master device, but both the master device and the slave device execute it. Do not care 5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection.
Page 93 CM: Command register DH: Device/Head register CH: Cylinder High register CL: Cylinder Low register SN: Sector Number register SC: Sector Count register Note: When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit).
Page 94 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) (R: Retry) At command completion (I/O registers contents to be read) (ST) Status information (DH)
Page 95 final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of (“number of sectors”/”block count”). If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled, the device rejects the READ MULTIPLE command with an ABORTED COMMAND error.
Page 96 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (*1) (SC) (ER) Error information If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register.
Page 97 At command issuance (I/O registers setting contents) (CM) (DH) (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)
Page 98 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)
Page 99 If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. At command issuance (I/O registers setting contents) (CM) (DH)
Page 100 Interface (6) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.
Page 101 At command issuance (I/O registers setting contents) (CM) (DH) (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)
Page 102 Interface A host system can select the following transfer mode using the SET FEATURES command. Multiword DMA transfer mode 0 to 2 Ultra DMA transfer mode 0 to 5 At command issuance (I/O registers setting contents) (CM) (DH) (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No.
Page 103 At command issuance (I/O registers setting contents) (CM) (DH) (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)
Page 104 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Note: Also executable in LBA mode. (10) SEEK (X’70’...
Page 105 At command issuance (I/O registers setting contents) (CM) (DH) (CH) Cylinder No. [MSB] / LBA (CL) Cylinder No. [LSB] / LBA (SN) Sector No. / LBA [LSB] (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) Cylinder No.
Page 106 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) Number of sectors/track (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) Number of sectors/track (ER) Error information (12) IDENTIFY DEVICE (X’EC’) The host system issues the IDENTIFY DEVICE command to read parameter information from the device.
Page 107 At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (13) IDENTIFY DEVICE DMA (X’EE’) When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command.
Page 108 Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 2) Word Value X’045A’ General Configuration *1 X’3FFF’ Number of Logical cylinders *2 X’xxxx’ Detailed Configuration *3 X’10’ Number of Logical Heads *2 X’0000’ Undefined X’3F’ Number of Logical sectors per Logical track *2 X’0000’...
Page 109 Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 2) Word Value X’0078’ Manufacturer’s recommended DMA transfer cycle time : 120 [ns] X’00F0’ Minimum PIO transfer cycle time without IORDY flow control : 240 [ns] X’0078’ Minimum PIO transfer cycle time with IORDY flow control : 120 [ns] 69-79 X’0000’...
Page 110 Bit 8: 1 = LBA Supported Bit 9: 1 = DMA Supported 5-36 Valid = 0 MHT2060AT MHT2040AT X’3FFF’ X’3FFF’ X’3FFF’ X’10’ X’10’ X’10’ X’3F’ X’3F’ X’3F’ X’6FC7C80’ X’4A85300’ MHT2030AT MHT2020AT X’3FFF’ X’3FFF’ X’10’ X’10’ X’3F’ X’3F’ X’37E3E40’ X’2542980’ C141-E192-01EN...
Page 111 *5 Word 50: Device capability Bit 15: Bit 14: Bit 13 to 1 Reserved Bit 0 Standby timer value '1' = Standby timer value of the device is the smallest value. *6 Word 51: PIO data transfer mode Bit 15-8: PIO data transfer mode Bit 7-0: Undefined...
Page 112 Interface Bit 7-0: Advance PIO transfer mode Bit 1: 1 = Mode 4 Bit 0: 1 = Mode 3 *11 WORD 80 Bit 15-7: Reserved Bit 6: 1 = ATA/ATAPI-6 supported Bit 5: 1 = ATA/ATAPI-5 supported Bit 4: 1 = ATA/ATAPI-4 supported Bit 3: 1 = ATA-3 supported Bit 2:...
Page 113 *13 WORD 83 Bits 15-14: Undefined Bit 13: Bit 12: Bit 11: Bit 10:* Bit 9: Bit 8: Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: *: Option (customizing) *14 WORD 84 Bit 15: Bit 14: Bit 13-2:...
Page 114 Interface Bit 10: '1' = Supports the Host Protected Area function. Bit 9: '1' = Supports the DEVICE RESET command. Bit 8: '1' = Enables the SERVICE interrupt. From the SET FEATURES command Bit 7: '1' = Enables the release interrupt. From the SET FEATURES command Bit 6: '1' = Enables the read cache function.
Page 115 Bit 0: '1' = Supports the Mode 0 *19 WORD 89 MHT2080AT = X'30': 96 minutes MHT2060AT = X'24': 72 minutes MHT2040AT = X'18': 48 minutes MHT2030AT = X'12': 36 minutes MHT2020AT = X'0C': 24 minutes *20 WORD 93 Bits 15: Bit 14: = '1' Bit 13: '1' = CBLID- is a higher level than VIH (80-conductor cable).
Page 116 Interface Bit 8: Bits 7-0: In the case of Device 0 (master drive), a valid value is set. Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2, 1: Bit 0: *21 WORD 94 Bit 15-8: X'FE' Recommended acoustic management value. Bit 7-0: X'XX' Current set value.
Page 117 Bit 5: '1' = Enhanced security erase supported Bit 4: '1' = Security counter expired Bit 3: '1' = Security frozen Bit 2: '1' = Security locked Bit 1: '1' = Security enabled Bit 0: '1' = Security supported (14) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed.
Page 118 Interface Table 5.5 Features register values and settable modes Features Register X’02’ Enables the write cache function. X’03’ Set the data transfer mode. *1 X’05’ Enables the advanced power management function. *2 X’42’ Enables the Acoustic management function. *3 X’55’ Disables read cache function.
Page 119 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) xx or *1~3 (FR) [See Table 5.5] At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information *1) Data Transfer Mode The host sets X’03’...
Page 120 Interface Multiword DMA transfer mode X Ultra DMA transfer mode X *2) Advanced Power Management (APM) The host writes the Sector Count register with the desired power management level and executes this command with the Features register X’05’, and then Advanced Power Management is enabled.
Page 121 *3) Automatic Acoustic Management (AAM) The host writes to the Sector Count register with the requested acoustic management level and executes this command with subcommand code 42h, and then Automatic Acoustic Management is enabled. The AAM level setting is preserved by the drive across power on, hardware and software resets. Performance mode (Fast Seek) Acoustic mode (Slow Seek) Abort...
Page 122 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) Sector count/block (FR) After power-on the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode. At command completion (I/O registers contents to be read) (ST) Status information (DH)
Page 123 SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command. This command allows the maximum address accessible by the user to be set in LBA or CHS mode. Upon receipt of the command, the device sets the BSY bit and saves the maximum address specified in the DH, CH, CL and SN registers.
Page 124 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information SET MAX SET PASSWORD (FR = 01h) This command requests a transfer of 1 sector of data from the host, and defines the contents of SET MAX password.
Page 125 At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Words 1 to 16 17 to 255 SET MAX LOCK (FR = 02h) The SET MAX LOCK command sets the device into SET_MAX_LOCK state. After this command is completed, any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected.
Page 126 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information SET MAX UNLOCK (FR = 03h) This command requests a transfer of single sector of data from the host, and defines the contents of SET MAX ADDRESS password.
Page 127 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information SET MAX FREEZE LOCK (FR=04h) The Set MAX FREEZE LOCK command sets the device to SET_MAX_Frozen state.
Page 128 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (17) READ NATIVE MAX ADDRESS (F8) This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command.
Page 129 At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information (18) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked).
Page 130 Interface Table 5.6 Diagnostic code Code X’01’ X’02’ X’03’ X’04’ X’05’ X’06’ X’8x’ attention: The device responds to this command with the result of power-on diagnostic test. At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST)
Page 131 (19) READ LONG (X’22’ or X’23’) This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command.
Page 132 Interface (20) WRITE LONG (X’32’ or X’33’) This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation.
Page 133 (21) READ BUFFER (X’E4’) The host system can read the current contents of the data buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt.
Page 134 Interface (22) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the data buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data.
Page 135 (23) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates interrupt even if the device has not fully entered the idle mode.
Page 136 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (24) IDLE IMMEDIATE (X’95’ or X’E1’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
Page 137 (25) STANDBY (X’96’ or X’E2’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. If the device has already spun down, the spin-down sequence is not implemented.
Page 138 Interface (26) STANDBY IMMEDIATE (X’94’ or X’E0’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the APS timer function. At command issuance (I/O registers setting contents) (CM) X’94’...
Page 139 (27) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt.
Page 140 Interface (28) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by the contents of the Sector Count register. The device sets the BSY bit and sets the following register value.
Page 141 (29) SMART (X’B0) This command predicts the occurrence of device failures depending on the subcommand specified in the FR register. If the FR register contains values that are not supported with the command, the Aborted Command error is issued. Before issuing the command, the host must set the key values in the CL and CH registers (4Fh in the CL register and C2h in the CH register).
Page 142 Interface Table 5.7 Features Register values (subcommands) and functions (1 of 3) Features Resister X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
Page 143 Table 5.7 Features Register values (subcommands) and functions (2 of 3) Features Resister X’D5’ SMART Read Log Sector: A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer.
Page 144 Interface Table 5.7 Features Register values (subcommands) and functions (3 of 3) Features Resister X’DA’ SMART Return Status: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values.
Page 145 At command completion (I-O registers setting contents) (ST) Status information (DH) (CH) Key-failure prediction status (C2h/2Ch) (CL) Key-failure prediction status (4Fh/F4h) (SN) (SC) (ER) Error information The attribute value information is 512-byte data; the format of this data is shown the following Table 5.8.
Page 146 Interface Table 5.8 Format of device attribute value data Byte Data format version number Attribute 1 07 to 0C 0E to 169 Attribute 2 to attribute 30 Off-line data collection status Self-test execution status 16C, 16D Off-line data collection execution time [sec.] Reserved Off-line data collection capability 170, 171...
Page 147 Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same. When a data format is changed, the data format version numbers are updated.
Page 148 Interface Status Flag If this bit is 1, it indicates normal operations are assured with the attribute when the attribute value exceeds the threshold value. If this bit is 1 (0), it indicates the attribute only updated by an on- line test (off-line test).
Page 149 Status Byte 00h or 80h Off-line data acquisition is not executed. 02h or 82h Off-line data acquisition has ended without an error. 04h or 84h Off-line data acquisition is interrupted by a command from the host. 05h or 85h Off-line data acquisition has ended before completion because of a command from the host.
Page 150 Interface Off-line data collection capability Indicates the method of off-line data collection carried out by the drive. If the off-line data collection capability is 0, it indicates that off-line data collection is not supported. If this bit is 1, it indicates that the SMART EXECUTE OFF- LINE IMMEDATE sub-command (FR register = D4h) is supported.
Page 151 Insurance failure threshold The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure. Table 5.10 Log Directory Data Format Byte SMART Logging Version Number of sectors of Address "01h" Reserved Number of sectors of Address "02h"...
Page 152 Interface Table 5.11 Data format of SMART Summary Error Log Byte Version of this function Pointer for the latest "Error Log Data Structure" 02 to 31 Error log data structure 3A to 3D 46 to 58 5C to 1C3 Error log data structure 2 to Error log data structure 5...
Page 153 Command data structure Indicates the command received when an error occurs. Error data structure Indicates the status register when an error occurs. Total number of drive errors Indicates total number of errors registered in the error log. Checksum Two's complementary for the lowest-order 1 byte that is obtained by adding 1 byte after another for as many as 511 bytes beginning from the top of the structure.
Page 154 Interface SMART Self-Test The host computer can issue the SMART Execute Off-line Immediate sub- command (FR Register = D4h) and cause the device to execute a self-test. When the self-test is completed, the device saves the SMART self-test log to the disk medium.
Page 155 Table 5.13 Selective self-test log data structure Offset 00h, 01h Data Structure Revision Number 02h...09h Test Span 1 0Ah...11h 12h...19h Test Span 2 1Ah...21h 22h...29h Test Span 3 2Ah...31h 32h...39h Test Span 4 3Ah...41h 42h...49h Test Span 5 4Ah...51h 52h...151h Reserved 152h...1EBh Vender Unique...
Page 156 Interface Table 5.14 Selective self-test feature flags Vendor specific (unused) When set to one, perform off-line scan after selective test Vendor specific (unused) When set to one, off-line scan after selective test is pending. When set to one, off-line scan after selective test is active. 5...15 Reserved Bit [l] shall be written by the host and returned unmodified by the device.
Page 157 Table 5.15 Contents of security password Word 1 to 16 17 to 255 At command issuance (I-O register contents)) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information C141-E192-01EN...
Page 158: 1F7 (Cm)
Interface (31) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command. The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command. Issuing this command during FROZEN MODE returns the Aborted Command error.
Page 159 Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET PASSWORD command and reset the user password. If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued, the Aborted Command error is returned. Issuing this command while in FROZEN MODE returns the Aborted Command error.
Page 160 Interface SECURITY ERASE UNIT FROZEN MODE is canceled when the power is turned off, or when hardware is reseted. If this command is reissued in FROZEN MODE, the command is completed and FROZEN MODE remains unchanged. Issuing this command during LOCKED MODE returns the Aborted Command error.
Page 161 (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (34) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.16 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.
Page 162 Interface Table 5.17 Relationship between combination of Identifier and Security level, and operation of the lock function Identifier Level User High Master High User Maximum Master Maximum At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information...
Page 163: At Command Issuance (I-O Register Contents)
(35) SECURITY UNLOCK This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.15 to the device. Operation of the device varies as follows depending on whether the host specifies the master password. When the master password is selected When the security level is LOCKED MODE is high, the password is compared with the master password already set.
Page 164: 1F6 (Dh)
Interface At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (36) FLUSH CACHE (E7) This command is used to order to write every write cache data stored by the device into the medium. BSY bit is held at "1" until every data has been written normally or an error has occurred.
Page 165: (St) Status Information
At command completion (I-O register contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (37) DEVICE CONFIGURATION (X'B1') Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register. The following table shows these Features register values.
Page 166: (Dh) X X X Dv
Interface At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information DEVICE CONFIGURATION RESTORE (FR=C0h) The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command.
Page 167 5.3 Host Commands DEVICE CONFIGURATION IDENTIFY (FR=C2h) The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure is shown in Table 5.18. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting.
Page 168 Interface Table 5.18 DEVICE CONFIGURATION IDENTIFY data structure Word Value X'0001' Data structure revision X'0007' Multiword DMA modes supported Reflected in IDENTIFY information "WORD63". Bit 15-3: Reserved Bit 2: Bit 1: Bit 0: X'003F' Ultra DMA modes supported Reflected in IDENTIFY information "WORD88". Bit 15-6: Reserved Bit 5: Bit 4:...
Page 169 (38) READ NATIVE MAX ADDRESS EXT (27H): Option (customizing) Description This command is used to assign the highest address that the device can initially set with the SET MAX ADDRESS EXT command. The maximum address is displayed in the CH, CL, SN registers of the device control register with HOB bit = 0, 1.
Page 170 Interface (39) SET MAX ADDRESS EXT (37H): Option (customizing) Description This command limits specifications so that the highest address that can be accessed by users can be specified only in LBA mode. The address information specified with this command is set in words 1, 54, 57, 58, 60, 61, and 100 to 103 of the IDENTIFY DEVICE command response.
Page 171 At command issuance (I/O registers setting contents) (CM) (DH) (CH) P SET MAX LBA (47-40) (CH) C SET MAX LBA (23-16) (CL) P SET MAX LBA (39-32) (CL) C SET MAX LBA (15-8) (SN) P SET MAX LBA (31-24) (SN) C SET MAX LBA (7-0) (SC) P (SC) C...
Page 172 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) P (CH) C (CL) P (CL) C (SN) P (SN) C (SC) P (SC) C (FR) P (FR) C C: Current P: Previous At command completion (I/O registers contents to be read) (ST) (DH) (CH) 1...
Page 173 (41) WRITE DMA EXT (35H): Option (customizing) Description This command is the extended command of the WRITE DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 174 Interface (42) READ DMA EXT (25H): Option (customizing) Description This command is the extended command of the READ DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 175 (43) WRITE MULTIPLE EXT (39H): Option (customizing) Description This command is the extended command of the WRITE MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 176 Interface (44) READ MULTIPLE EXT (29H): Option (customizing) Description This command is the extended command of the READ MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 177 (45) WRITE SECTOR (S) EXT (34H): Option (customizing) Description This command is the extended command of the WRITE SECTOR (S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 178 Interface (46) READ SECTOR (S) EXT (24H): Option (customizing) Description This command is the extended command of the READ SECTOR (S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 179: 1F5 (Ch)
(47) DOWNLOAD MICRO CODE (92H) At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) This command rewrites the microcode of the device (firmware). When this command is accepted, the device does beginning the data transfer of the microcode or the microcode rewriting according to Subcommand code (Rewriting is also possible simultaneously with the data transfer).
Page 180 Interface Table 5.19 Operation of DOWNLOAD MICRO CODE Host Command Subcommand code Sector count (FR Reg) (SN, SC Reg) 0000h xxxxh 0000h xxxxh Excluding 01h and 07h **: In the following cases, Subcommand code=07h returns Abort as an error though becomes Microcode rewriting execution specification. 1) Abnormality of the transmitted Microcode data is detected.
Page 181: Error Posting
5.3.3 Error posting Table 5.21 lists the defined errors that are valid for each command. Table 5.21 Command code and parameters (1 of 2) Command name READ SECTOR(S) WRITE SECTOR(S) READ MULTIPLE WRITE MULTIPLE READ DMA WRITE DMA WRITE VERIFY READ VERIFY SECTOR(S) RECALIBRATE SEEK...
Page 182 Interface Table 5.21 Command code and parameters (2 of 2) Command name SLEEP CHECK POWER MODE SMART SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK FLUSH CACHE DEVICE CONFIGURATION READ NATIVE MAX ADDRESS SET MAX ADDRESS EXT FLUSH CACHE EXT WRITE DMA EXT...
Page 183: Command Protocol
5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1.
Page 184 Interface words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting. Figure 5.3 shows an example of READ SECTOR(S) command protocol, and Figure 5.4 shows an example protocol for command abort. Figure 5.3 Read Sector(s) command protocol For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal.
Page 185: Pio Data Transferring Commands From Host To Device
device to starting of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed.
Page 186 Interface The execution of these commands includes the transfer one or more sectors of data from the host to the device. In the WRITE LONG command, 516 bytes are transferred. Following shows the protocol outline. a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers.
Page 187: Commands Without Data Transfer
40 ms Figure 5.5 WRITE SECTOR(S) command protocol For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer.
Page 188 Interface SEEK READY VERIFY SECTOR(S) EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE SET MAX ADDRESS (EXT) READ NATIVE MAX ADDRESS (EXT) IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE SMART DISABLE OPERATION SMART ENABLE/DISABLE AUTOSAVE SMART ENABLE OPERATION SMART EXECUTE OFFLINE IMMEDIATE SMART RETURN STATUS...
Page 189: Other Commands
5.4.4 Other commands READ MULTIPLE (EXT) SLEEP WRITE MULTIPLE (EXT) See the description of each command. 5.4.5 DMA data transfer commands READ DMA (EXT) WRITE DMA (EXT) Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.
Page 190 Interface The interrupt processing for the DMA transfer differs the following point. The interrupt processing for the DMA transfer differs the following point. a) The host writes any parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head register. b) The host initializes the DMA channel c) The host writes a command code in the Command register.
Page 191 5.4 Command Protocol Figure 5.7 Normal DMA data transfer C141-E192-01EN 5-117...
Page 192: Ultra Dma Feature Set
Interface 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only.
Page 193: Phases Of Operation
device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.
Page 194: The Data In Transfer
Interface 8) The device may assert DSTROBE t Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst. 9) The host shall negate STOP and assert HDMARDY- within t asserting DMACK-.
Page 195: Terminating An Ultra Dma Data In Burst
NOTE - The host shall not immediately assert STOP to initiate Ultra 3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge. b) Host pausing an Ultra DMA data in burst 1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.
Page 196 Interface 6) The host shall drive DD (15:0) no sooner than t negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5): 7) If DSTROBE is negated, the device shall assert DSTROBE within t after the host has asserted STOP.
Page 197 after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t for the device. 5) The host shall assert STOP no sooner than t HDMARDY-.
Page 198: Ultra Dma Data Out Commands
Interface 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
Page 199: Pausing An Ultra Dma Data Out Burst
2) The host shall generate an HSTROBE edge to latch the new word no sooner than t after changing the state of DD (15:0). The host shall generate an HSTROBE edge no more frequently than t Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t 3) The host shall not change the state of DD (15:0) until at least t generating an HSTROBE edge to latch the data.
Page 200: Terminating An Ultra Dma Data Out Burst
Interface 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
Page 201 b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.
Page 202: Ultra Dma Crc Rules
Interface 13) The host shall neither negate STOP nor HSTROBE until at least t negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.
Page 203: Series Termination Required For Ultra Dma
The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.
Page 204: Timing
Interface 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IORDY Symbol Timing parameter Cycle time Data register selection setup time for DIOR-/DIOW- Pulse width of DIOR-/DIOW- Recovery time of DIOR-/DIOW- Data setup time for DIOW-...
Page 205: Multiword Data Transfer
5.6.2 Multiword data transfer Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system. Symbol Timing parameter Cycle time Pulse width of DIOR-/DIOW- Data Access time for DIOR- Data hold time for DIOR- Data setup time for DIOR-/DIOW- Data hold time for DIOW- DMACK setup time for DIOR-/DIOW- CS (1:0) Available time for DIOR-/DIOW-...
Page 206: Ultra Dma Data Transfer
Interface 5.6.3 Ultra DMA data transfer Figures 5.11 through 5.20 define the timings associated with all phases of Ultra DMA bursts. Table 5.23 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
Page 207: Ultra Dma Data Burst Timing Requirements
5.6.3.2 Ultra DMA data burst timing requirements Table 5.23 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 (in ns) (in ns) (in ns) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 2CYCTYP 2CYC DZFS...
Page 208 Interface Table 5.23 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 MODE 2 (in ns) (in ns) (in ns) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX IORDYZ ZIORDY *1: Except for some instances of t that apply to host signals only, the parameters t to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding.
Page 209 Table 5.24 Ultra DMA sender and recipient timing requirements MODE 0 MODE 1 MODE 2 (in ns) (in ns) (in ns) NAME MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 14.7 DSIC DHIC 72.9 50.9 33.9 DVSIC DVHIC *1: The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input...
Page 210: Sustained Ultra Dma Data In Burst
Interface 5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DSTROBE at device DVHIC DD(15:0) at device DSTROBE at host DHIC DD(15:0) at host Note: DD (15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.
Page 211: Host Pausing An Ultra Dma Data In Burst
5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) (device) Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t 2) After negating HDMARDY-, the host may receive zero, one, two or three more data words from the device.
Page 212: Device Terminating An Ultra Dma Data In Burst
Interface 5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.
Page 213: Host Terminating An Ultra Dma Data In Burst
5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.
Page 214: Initiating An Ultra Dma Data Out Burst
Interface 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) ZIORDY DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK- are asserted.
Page 215: Sustained Ultra Dma Data Out Burst
5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. HSTROBE at host DVHIC DD(15:0) at host HSTROBE at device DHIC DD(15:0) at device Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.
Page 216: Device Pausing An Ultra Dma Data Out Burst
Interface 5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t 2) After negating DDMARDY-, the device may receive zero, one two or three more data words from the host.
Page 217: Host Terminating An Ultra Dma Data Out Burst
5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.
Page 218: Device Terminating An Ultra Dma Data Out Burst
Interface 5.6.3.11 Device terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.
Page 219: Power-On And Reset
5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) [Master device] DASP- [Slave device]...
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Page 221: Chapter 6 Operations
CHAPTER 6 Operations Device Response to the Reset Power Save Defect Processing Read-Ahead Cache Write Cache C141-E192-01EN...
Page 222: Device Response To The Reset
Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for least 500 ms to confirm presence of a slave device (device 1).
Page 223: Response To Hardware Reset
Power on Master device Power On Reset- Status Reg. BSY bit Checks DASP- for up to 500 ms. Slave device Power On Reset- BSY bit PDIAG- DASP- Figure 6.1 Response to power-on Note: Figure 6.1 has a assumption that the device is kept on the power-off condition for more than 5 sec before the device power is turned on.
Page 224 Operations After the slave device receives the hardware reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below: DASP- signal: Asserted within 450 ms. PDIAG- signal: Negated within 1 ms and asserted within 30 seconds. The asserted PDIAG-signal is negated 30 seconds after it is asserted if the command is not received.
Page 225: Response To Software Reset
6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully. After the slave device receives the software reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below:...
Page 226: Response To Diagnostic Command
Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self- diagnosis successfully.
Page 227: Power Save
6.2 Power Save The host can change the power consumption state of the device by issuing a power command to the device. 6.2.1 Power save mode There are five types of power consumption state of the device including active mode where all circuits are active. Active mode Active idle mode Low power idle mode...
Page 228 Operations Upon receipt of a hard reset Upon receipt of Idle/Idle Intermediate (4) Standby mode In this mode, the spindle motor has stopped from the low power idle state. The device can receive commands through the interface. However if a command with disk access is issued, response time to the command under the standby mode takes longer than the active, active idle, or low power idle mode because the access to the disk medium cannot be made immediately.
Page 229: Defect Processing
6.2.2 Power commands The following commands are available as power commands. IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SET FEATURES (APM setting) 6.3 Defect Processing This device performs alternating processing where the defective sector is alternated with the spare area depending on media defect location information. The media defect location information is registered in the system space specified for the user area according to the format at shipment of the media from the plant.
Page 230 Operations 6.3.2 Alternating processing for defective sectors The following two types of technology are used for alternating processing: (1) Sector slip processing In this method, defective sectors are not used (thereby avoiding the effects of defects), and each defective sector is assigned to the next contiguous sector that is normal.
Page 231 Automatic alternating processing This technology assigns a defective sector to a spare sector of an spare cylinder for alternate assignment. This device performs automatic alternating processing in the event of any of the following errors. Automatic alternating processing is attempted for read error recovery by heightening the ECC correction capability while a read error retry is in progress.
Page 232 Operations 6.4 Read-ahead Cache Read-ahead Cache is the function for automatically reading data blocks upon completion of the read command in order to read data from disk media and save data block on a data buffer. If a subsequent command requests reading of the read-ahead data, data on the data buffer can be transferred without accessing the disk media.
Page 233 6.4.2 Caching operation The caching operation is performed only when the commands listed below are received. If any of the following data are stored on the data buffer, the data is sent to the host system. All of the sector data that this command processes. A part of the sector data including the start sector, that this command processes.
Page 234 Operations READ LOG EXT READ BUFFER WRITE LONG WRITE LOG EXT WRITE BUFFER RECALIBRATE FORMAT TRACK IDENTIFY COMPONENT SET FEATURES SECURITY ERASE UNIT DEVICE CONFIGURATION DOWNLOAD MICROCODE UNSUPPORT COMMAND (INVALID COMMAND) 1)-2 Commands that partially invalidate caching data (When data in the buffer or on media is overwritten, the overwritten data is invalidated.) READ DMA / READ MULTIPLE / READ SECTOR (s) READ DMA EXT / READ MULTIPLE EXT / READ SECTOR (s) EXT...
Page 235: Using The Read Segment Buffer
6.4.3 Using the read segment buffer Methods of using the read segment buffer are explained for following situations. 6.4.3.1 Miss-hit In this situations, the top block of read requested data is not stored at all in the data buffer. As a result, all of the read requested data is read from disk media. 1) HAP (host address pointer) and DAP (disk address pointer) are defined in the head of the segment allocated from Buffer.
Page 236 Operations 4) The following cache valid data is for the read command that is executed next: 6.4.3.2 Sequential Hit When the read command that is targeted at a sequential address is received after execution of the read commands is completed, the read command transmits the Read requested data to the host system continuing read-ahead without newly allocating the buffer for read.
Page 237 4) The following cache valid data is for the read command that is executed next: 6.4.3.3 Full hit In this situation, all read requested data is stored in the data buffer. Transfer of the read requested data is started from the location where hit data is stored. For data that is a target of caching and remains before a full hit, the data is retained when execution of the command is completed.
Page 238 Operations 6.4.3.4 Partial hit In this situation, a part of read requested data including the top sector is stored in the data buffer. A transfer of the read requested data starts from the address where the data that is hit is stored until the top sector of the read requested data. Remaining part of insufficient data is read then.
Page 239: Write Cache
6.5 Write Cache Write Cache is the function for reducing the command processing time by separating command control to disk media from write control to disk media. When Write Cache is permitted, the write command can be keep receiving as long as the space available for data transfers remains free on the data buffer.
Page 240 Operations <Exception> If a Reset or command is received while a transfer of one sector of data is in progress, data is not written in the sector of the media where the interruption occurred, and sectors accepted before interruption occurred is written in the medium.
Page 241 6.5 Write Cache determining which command caused the error. (An error report is not issued to the host if automatic alternating processing for the error is performed normally.) Therefore, the host cannot execute a retry for the unrecoverable error while Write Cache is enabled. Be very careful on this point when using this function.
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Page 243 Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors.
Page 244 Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
Page 245 Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
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Page 247: Acronyms And Abbreviations
Acronyms and Abbreviations ABRT Aborted command Automatic idle control AMNF Address mark not found AT attachment American wire gage Bad block detected BIOS Basic input-output system CORR Corrected data Cylinder high register Cylinder low register Command register Current sense register Current start/stop Cylinder register dB A-scale weighting...
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Page 249 active idle mode 6-7 active mode 6-7 alternating processing, automatic 6-11 for defective sector 6-10 for defective sector 6-10 area, spare 6-9 assignment processing, alternate cylinder 6-10 automatic alternating processing 6-11 blower 4-3 caching operation 6-13, 6-19 command, sequential 6-16 command, target of caching 6-13 command that is target of caching 6-13, 6-19...
Page 250 Index pausing, host Ultra DMA data in burst 5-137 PIO data transfer 5-130 timing 5-130 power commands 6-9 power-on 5-145 timing 5-145 power save 6-7 mode 6-7 processing, defect 6-9 processing, sector slip 6-10 processing, track slip 6-10 read-ahead 6-12 cache 6-12 operation 6-12 READ DMA 6-13...
Page 251 We would appreciate your comments and suggestions regarding this manual. Manual code C141-E192-01EN Manual name MHT2080AT, MHT2060AT, MHT2040AT MHT2030AT, MHT2020AT DISK DRIVES PRODUCT MANUAL Please mark each item: E(Excellent), G(Good), F(Fair), P(Poor). General appearance Technical level Organization Clarity Accuracy Comments & Suggestions List any errors or suggestions for improvement.
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Page 253 MHT2080AT, MHT2060AT, MHT2040AT MHT2030AT, MHT2020AT C141-E192-01EN DISK DRIVES PRODUCT MANUAL MHT2080AT, MHT2060AT, MHT2040AT MHT2030AT, MHT2020AT C141-E192-01EN DISK DRIVES PRODUCT MANUAL...
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Fujitsu MHT2020AT Product Manual

Table of Contents

CHAPTER 1 Device Overview

CHAPTER 2 Device Configuration

CHAPTER 3 Installation Conditions

CHAPTER 4 Theory of Device Operation

CHAPTER 5 Interface

Table of Contents

Table of Contents

CHAPTER 6 Operations

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