Block Diagram And Circuit Description - Sony DNW-7 Maintenance Manual

Circuit Description
(1) Camera process system
(DCP-31/1 and ES-11 boards)
. DCP-31/1 board
The DCP-31/1 board consists of the following blocks:
(1) Receiver of R/G/B signals from the CCD block, A/D
converters for R/G/B signals, Digital processor to
convert to the digital component signals, and D/A
converter so as to output the Y/R-Y/B-Y/VF signals
to the ES-11 board.
(2) Driver block which adds the character data to the
composite signal supplied from the ES-11 board,
and outputs the added signal.
(3) Rate converter
(4) Signal processor for viewfinder
The analog R/G/B signals which are input from the CCD
block are passed through the respective pre-filters having
the corresponding sampling frequencies (WIDE/NOR-
MAL), then are converted by the A/D converter to the
10-bit digital R/G/B signals of 14 MHz (NORMAL) or
18 MHz (WIDE) rate respectively.
The digital R/G/B signals after A/D conversion are input
to the pre-process IC. This IC detect the average value
and peak value of the video signals detected which are
required by the AUTO operation system of the camera
such as auto black balance, auto white balance and auto
iris and so on.
The pre-process IC outputs the black and white shading
correction signals (G BSH, R BSH, B BSH/G WSH, R
WSH and B WSH), feed-back clamp control signal (G
FB, R FB and B FB) and TEST SAW signal to the CCD
block.
The digital G and R signals output from the pre-process
IC are passing through the 1H delay lines to generates
the V details, and input to the processor IC. But digital B
signal output from the pre-process IC is input the
processor IC directly.
In the processor IC, the digital R/G/B signals are up-
converted to 28 MHz (NORMAL) or 36 MHz (WIDE)
signal respectively, the matrix and the detail signals are
added, the flare compensation, pedestal control, gamma
correction, knee correction and white clip are applied,
then converted to the digital component signals (Y, R-Y
and B-Y).
DNW-7/90/90WS
Section 4

Block Diagram and Circuit Description

The processor IC has the function of the output signal
switch circuit which switches between the built-in color
signal and the main line signal. The processor IC also
has the Y, R/G/B video outputs circuit for viewfinder.
The output signals of the processor IC are D/A converted
and send to the VF or TEST OUT terminal. The view-
finder output circuit has the signal selector function
which enables monitoring the video signal supplied to
the GENLOCK IN connector or the RET video signal
when a CCU is connected, using the monitor select IC.
The digital component signal output from the processor
IC is passed through the CN-1193 board
the rate converter and D/A converter. The digital compo-
nent signal is rate-converted to 27 MHz by rate convert-
er, and output to the DVP-1 board. The other digital
component signal is D/A converted, and resultant analog
component signals (Y, R-Y, B-Y) are output to ES-11
board.
The average value and peak value of the video signal
which are detected in the pre-process IC are sent to the
camera CPU and the control CPU via I/O expander
through the 4-bit LSI data bus.
After processing the detected values by the camera CPU,
the control data is sent to the processor IC and VA-191/
167 board in CCD block through data bus and SAD
(CCD) signal.
The control CPU performs the various controls of the
camera block in accordance with the commands stored in
the ROM. The control CPU decodes the variable control
data which are detected in pre-process IC, function
switch command and analog data, and then output the
various control signals.
The control CPU writes the status information and the
self-diagnostics information to the character generator
and outputs these data as the character data.
Connection with the external equipment such as RM-P9
(optional) and VA-DN1 (optional) is made possible by
the transmitter/receiver IC.
*1
, and input to
4-1