ECS KM400-M2 Manual page 37

DRAM Clock (By SPD)
This item enables you to manually set the DRAM Clock. We recommend that you leave this
item at the default value.
DRAM Timing (Auto By SPD)
Set this to the default value to enable the system to automatically set the SDRAM timing by
SPD (Serial Presence Detect). SPD is an EEPROM chip on the DIMM module that stores
information about the memory chips it contains, including size, speed, voltage, row and
column addresses, and manufacturer. If you disable this item, you can use the following three
items to manually set the timing parameters for the system memory.
• DRAM CAS Latency (2.5): Enables you to select the CAS latency time in
HCLKs of 2/2 or 3/3. The value is set at the factory depending on the DRAM
installed. Do not change the values in this field unless you change specifications
of the installed DRAM or the installed CPU.
• Bank Interleave (Disabled): Enable this item to increase memory speed.
When enabled, separate memory banks are set for odd and even addresses and the
next byte of memory can be accessed while the current byte is being refreshed.
• Precharge to Active (3T): This item is used to designate the minimum Row
Precharge time of the SDRAM devices on the module.
DRAM must continually be refreshed or it will lose its data. Normally, DRAM is
refreshed entirely as the result of a single request. This option allows you to
determine the number of CPU clocks allocated for the Row Address Strobe (RAS)
to accumulate its charge before the DRAM is refreshed. If insufficient time is
allowed, refresh may be incomplete and data lost.
• Active to Precharge(Tras)(7T): This item specifies the number of clock
cycles needed after a bank active command before a precharge occur.
• Active to CMD (3T): This item specifies the minimum required delay between
activation of different rows.
DRAM Burst Length(4)
This item describes which burst lengths are supported by the devices on the motherboard. 1
level can provide faster performance but may result in instability whereas 8 level gives the
most stable but slowest performance.
DRAM Command Rate (2T Command)
This item enables you to specify the waiting time for the CPU to issue the next command
after issuing the command to the DDR memory. We recommend that you leave this item at
the default value.
Press <Esc> to return to the Advanced Chipset Features page.
Using BIOS
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