Advanced Chipset Features; Dram Timing Selectable; Cas Latency Time; Active To Precharge Delay - IBASE Technology IB800 User Manual

Advanced Chipset Features

This Setup menu controls the configuration of the chipset.
CMOS Setup Utility – Copyright © 1984-2001 Award Software

DRAM Timing Selectable

CAS Latency Time

Active to Precharge Delay

DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
DRAM Data Integrity Mode
Memory Frequency For
DRAM Read Thermal Mgmt
System BIOS Cacheable
Video BIOS Cacheable
Video RAM Cacheable
Memory Hole At 15M-16M
Delayed Transaction
Power-Supply Type
AGP Graphics Aperture Size
Delay Prior to Thermal
ICH2 ISA Enable
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected.
The default is By SPD.
CAS Latency Time
You can select CAS latency time in HCLKs of 2/2 or 3/3. The system
board designer should set the values in this field, depending on the
DRAM installed. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU. The choices
are 2 and 3.
Active to Precharge Delay
The default setting for the Active to Precharge Delay is 6.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address
Strobe) and CAS (Column Address Strobe) signals. This delay occurs
when the SDRAM is written to, read from or refreshed. Reducing the
delay improves the performance of the SDRAM.
DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to accumulate
its charge before the SDRAM refreshes. The default setting for the Active
to Precharge Delay is 3.
Advanced Chipset Features
By SPD
3
6
3
3
Non-ECC
Auto
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
ATX
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Enabled
IB800 User' s Manual
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