Pci Delay Transaction; Memory Hole; System Bios Cacheable; Video Ram Cacheable - Albatron KX400+ Pro-C User Manual

PCI Delay Transaction

The chipset has an embedded 32-bit poste write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification.
Options: Disabled (default)、Enabled

Memory Hole

When enabled, you can reserve an area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. Refer to the user documentation of
the peripheral you are installing for more information. Options: Disabled (default)、
Enabled

System BIOS Cacheable

When enabled, access to system BIOS ROM addressed at F0000H-FFFFFH is
cached, provided that the cache controller is enabled. Options: Enabled、Disabled
(default)

Video RAM Cacheable

Select enabled to allow caching of the video BIOS, resulting in better system
performance. However, if any program writes to this memory area, a system error
may result.
Options: Enabled、Disabled (default)
PnP/PCI Configurations

PNP OS Installed

When set to YES, BIOS will only initialize the PnP cards used for the boot sequence
(VGA, IDE, SCSI). The rest of the cards will be initialized by the PnP operating
®
system like Window 95. When set to NO, BIOS will initialize all the PnP cards. For
non-PnP operating systems (DOS, Netware), this option must set to NO. Options: No
(default)、Yes

Reset Configuration Data

Default is "Disabled". Select "Enabled" to reset Extended System Configuration Data
(ESCD) when you exit Setup if you have installed a new add-on and the system
reconfiguration has caused such a serious conflict that the OS cannot boot.
Options: Disabled (default)、Enabled

Resources Controlled By

BIOS can automatically configure all the boot and Plug and Play compatible devices.
If you choose Auto, you cannot select IRQ DMA and memory base address fields,
since BIOS automatically assigns them. Options: Auto <ESCD> (default)、Manual
KX400+ series mainboard
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