SOYO SY-7VBA133U User Manual page 69

BIOS Setup Utility
CHIPSET FEATURES SETUP (Continued)
CHIPSET Setting
FEATURES
Disabled
PCI Master 0
WS Write
Enabled
PCI Delay Disabled
Transaction
Enabled
PCI#2 Access Disabled
#1 Retry
Enabled
AGP Master 1 Disabled
WS Write
Enabled
Disabled
AGP Master 1
WS Read
Enabled
Memory Disabled
Parity/ECC
Enabled
Check
Description
When Enabled, writes to the PCI
bus are executed with zero wait
states.
The chipset has an embedded 32-bit
posted write buffer to support delay
transactions cycles. Select Enabled
to support compliance with PCI
specification version 2.1.
When disabled, PCI#2 will not be
disconnected until access finishes
(difault). When enabled, PCI#2 will
be disconnected if max retries are
attempted without success.
When Enabled, writes to the
AGP(Accelerated Graphics Port) are
executed with one wait states.
When Enabled, read to the AGP
(Accelerated Graphics Port) are
executed with one wait states.
This item enabled to detect the
memory parity and Error Checking
& Correcting.
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SY-7VBA133U
Note
Default
Default
Default
Default
Default
Default