Chipset - SOYO SY-7VBA133U User Manual

Motherboard Description SY-7VBA133U

1-9 CHIPSET

VT82C694T
The VT82C694T is a high performance, cost-effective and energy efficient
chip set for the implementation of AGP / PCI / ISA desktop personal
computer systems from 66 MHz, 100 MHz and 133 MHz based on 64-bit
Socket-370 (Intel Celeron, and Intel Tualatin) and Slot-1 (Intel Pentium III)
super-scalar processors.
The VIA 694T chip set consists of the VT82C694T system controller (520
pin BGA) and the VT82C686B PCI to ISA bridge (352 pin BGA). The
system controller provides superior performance between the CPU,
DRAM, AGP bus, and PCI bus with pipelined, burst, and concurrent
operation.
The VT82C694T supports eight banks of DRAMs up to 1.5GB. The
DRAM controller supports standard Fast Page Mode (FPM) DRAM,
EDO-DRAM, Synchronous DRAM (SDRAM) and Virtual Channel
SDRAM (VC SDRAM), in a flexible mix / match manner. The
Synchronous DRAM interface allows zero wait state bursting between the
DRAM and the data buffers at 66/100/133 MHz. The eight banks of
DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M /
16M / 32MxN DRAMs. The DRAM controller also supports optional
ECC (single-bit error correction and multi-bit detection) or EC (error
checking) capability separately selectable on a bank-by-bank basis. The
DRAM controller can run at either the host CPU bus frequency (66 /100
/133 MHz) or at the AGP bus frequency (66 MHz) with built-in PLL
timing control.
The VT82C694T system controller also supports full AGP v2.0 capability
for maximum bus utilization including 2x and 4x mode transfers, SBA
(SideBand Addressing), Flush/Fence commands, and pipelined grants. An
eight level request queue plus a four level post-write request queue with
thirty-two and sixteen quadwords of read and write data FIFO's
respectively are included for deep pipelined and split AGP transactions. A
single-level GART TLB with 16 full associative entries and flexible CPU /
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