SOYO SY-7VBA133U User Manual page 14

Motherboard Description

Two-bank interleaving for 16Mbit SDRAM support

Two-bank and four bank interleaving for 64Mbit SDRAM support

Supports maximum 8-bank interleave (i.e., 8 pages open
simultaneously); banks are allocated based on LRU

Independent SDRAM control for each bank

Seamless DRAM command scheduling for maximum DRAM bus
utilization (e.g., precharge other banks while accessing the current
bank)

Four cache lines (16 quadwords) of CPU to DRAM write buffers

Four cache lines of CPU to DRAM read prefetch buffers

Read around write capability for non-stalled CPU read

Speculative DRAM read before snoop result

Burst read and write operation

x-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM from CPU
or from DRAM controller

x-1-1-1-1-1-1-1 back-to-back accesses for SDRAM

BIOS shadow at 16KB increment

Decoupled and burst DRAM refresh with staggered RAS timing

CAS before RAS or self refresh
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SY-7VBA133U