Phases Of Operation; Ultra Dma Data In Commands - Fujitsu MHW2080AT Product Manual

Interface
Both the host and device perform a CRC function during an Ultra DMA burst. At
the end of an Ultra DMA burst the host sends the its CRC data to the device. The
device compares its CRC data to the data sent from the host. If the two values do
not match the device reports an error in the error register at the end of the
command. If an error occurs during one or more Ultra DMA bursts for any one
command, at the end of the command, the device shall report the first error that
occurred.

5.5.2 Phases of operation

An Ultra DMA data transfer is accomplished through a series of Ultra DMA data
in or data out bursts. Each Ultra DMA burst has three mandatory phases of
operation: the initiation phase, the data transfer phase, and the Ultra DMA burst
termination phase. In addition, an Ultra DMA burst may be paused during the data
transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of
these phases, 5.6 defines the specific timing requirements). In the following rules
DMARDY- is used in cases that could apply to either DDMARDY- or
HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE
or HSTROBE. The following are general Ultra DMA rules.
a) An Ultra DMA burst is defined as the period from an assertion of DMACK-
by the host to the subsequent negation of DMACK-.
b) A recipient shall be prepared to receive at least two data words whenever it
enters or resumes an Ultra DMA burst.

5.5.3 Ultra DMA data in commands

5.5.3.1 Initiating an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.3.1 and 5.6.3.2 for specific timing requirements):
1) The host shall keep DMACK- in the negated state before an Ultra DMA burst
is initiated.
2) The device shall assert DMARQ to initiate an Ultra DMA burst. After
assertion of DMARQ the device shall not negate DMARQ until after the first
negation of DSTROBE.
3) Steps (3), (4) and (5) may occur in any order or at the same time. The host
shall assert STOP.
4) The host shall negate HDMARDY-.
5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep
CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at
the end of the burst.
6) Steps (3), (4) and (5) shall have occurred at least t
DMACK-. The host shall keep DMACK- asserted until the end of an Ultra
DMA burst.
5-138
before the host asserts
ACK
C141-E250