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[Signal]
CS0-
CS1-
DA 0-2
KEY
PDIAG-
CBLID-
DASP-
IORDY
DDMARDY-
DSTROBE
CSEL
DMACK-
C141-E250
[I/O]
I
Chip select signal decoded from the host address bus. This signal
is used by the host to select the command block registers.
I
Chip select signal decoded from the host address bus. This signal
is used by the host to select the control block registers.
I
Binary decoded address signals asserted by the host to access task
file registers.
-
Key pin for prevention of erroneous connector insertion
I/O
This signal is an input mode for the master device and an output
mode for the slave device in a daisy chain configuration. This
signal indicates that the slave device has been completed self-
diagnostics.
This signal is pulled up to +5 V through 10 kΩ resistor at each
device.
I/O
This signal is used to detect the type of cable installed in the
system.
This signal is pulled up to +5 V through 10 kΩ resistor at each
device.
I/O
This is a time-multiplexed signal that indicates that the device is
active and a slave device is present.
This signal is pulled up to +5 V through 10 kΩ resistor at each
device.
O
This signal requests the host system to delay the transfer cycle
when the device is not ready to respond to a data transfer request
from the host system.
O
Flow control signal for Ultra DMA data Out transfer (WRITE
DMA command). This signal is asserted by the device to inform
the host that the device is ready to receive the Ultra DMA data Out
transfer. The device can negate the DDMARDY- signal to
suspend the Ultra DMA data Out transfer.
O
Data In Strobe signal from the device during Ultra DMA data In
transfer. Both the rising and falling edges of the DSTROBE signal
latch data from Data 15-0 into the host. The device can suspend
the inversion of the DSTROBE signal to suspend the Ultra DMA
data In transfer.
I
This signal to configure the device as a master or a slave device.
−
When CSEL signal is grounded, the IDD is a master device.
−
When CSEL signal is open, the IDD is a slave device.
This signal is pulled up with 240 kΩ resistor at each device.
I
The host system asserts this signal as a response that the host
system receives data or to indicate that data is valid.
5.1 Physical Interface
[Description]
5-5
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