Sony UCP-8060E Maintenance Manual page 38

IC
[|IC|]
AT45DB321B-TI (ATMEL)
32M-BIT FLASH MEMORY
—TOP VIEW—
PIN
1 32 NO.
1
2 31
2
3
3 30
4
5
4 29
6
7
5 28
8
9
6 27
10
11
7 26
12
13
8 25
14
15
9 24
16
10 23
INPUTS
CS
11 22
RESET
12 21
SCK
SI
WP
13 20
14 19
OUTPUTS
BUSY
15 18
RDY
SO
16 17
OTHER
NC
IM100-TQ144C (IMSYS)
MICRO CONTROLLER
—TOP VIEW—
109
110
115
120
125
130
135
140
144
3-2
PIN
I/O SIGNAL I/O SIGNAL
NO.
BUSY
O 17 — NC
RDY/
RESET
I 18 — NC
WP
I 19 — NC
— NC 20 — NC
— NC 21 — NC
— NC 22 — NC
— V 23 — NC
CC
— 24 — NC
GND
— NC 25 — NC
— NC 26 — NC
— NC 27 — NC
— NC 28 — NC
CS
I 29 — NC
I SCK 30 — NC
I SI 31 — NC
O SO 32 — NC
: CHIP SELECT
: CHIP RESET
: SERIAL CLOCK
: SERIAL
: WRITE PROTECT
: BUSY
: READY
: SERIAL
: NO CONNECTION
72
70
65
60
55
50
45
40
37
PIN PIN
I/O SIGNAL I/O
NO. NO.
— O
1 V 49
CC
I O
2 MTEST 50
— O
3 R.GND 51
4 I MRES1 52 —
O —
5 MRES2 53
— I/O
6 V 54
CCR
I I/O
7 MSDIN 55
O I/O
8 MSDOUT 56
9 O TYA_PD7 57 I/O
O I/O
10 TYA_PD6 58
11 O TYA_PD5 59 I/O
O I/O
12 TYA_PD4 60
O I/O
13 TYA_PD3 61
O —
14 TYA_PD2 62
O —
15 TYA_PD1 63
16 O TYA_PD0 64 I/O
— I/O
17 GND 65
— I/O
18 V 66
CC
O I/O
19 TDA_PE7 67
O I/O
20 TDA_PE6 68
21 O TDA_PE5 69 I/O
O I/O
22 TDA_PE4 70
23 O TDA_PE3 71 I/O
O —
24 TDA_PE2 72
O —
25 TDA_PE1 73
O I/O
26 TDA_PE0 74
— I/O
27 GND 75
28 — V 76 I/O
CC
DWE
O I/O
29 77
DRAS3
O I/O
30 78
DRAS2
O I/O
31 79
DRAS1
O I/O
32 80
DRAS0
33 O 81 I/O
DUCAS
O I/O
34 82
DLCAS
35 O 83 I/O
— I/O
36 GND 84
— I/O
37 V 85
CC
O I/O
38 DA11 86
O I/O
39 DA10 87
40 O DA9 88 I/O
O I/O
41 DA8 89
O —
42 DA7 90
O —
43 DA6 91
— I/O
44 GND 92
45 — V 93 I/O
CC
O I/O
46 DA5 94
47 O DA4 95 I/O
O I/O
48 DA3 96
INPUTS
CLK_SEL
: SELECT CLOCK SOURCE (LOW : 16, HIGH : 33)
IDREQ3
IDREQ0
- : DMA REQUEST CH0 - CH3
MIRQ0 MIRQ1
,
: INTERRUPT REQUEST (0: HIGHEST PRIO)
MRES1
: RTC XTAL 32.768 kHz
MRESET
: SYSTEM RESET
MSDIN
: SERIAL DATA FOR SWITCH DEBUG
MTEST : FACTORY TEST
MX1_CK
: XTAL 16.67/33 MHz
T_EN : TEST ENABLE FOR PLL
T_VCOM
: TEST (SET VCO MAX FREQ.)
TENABLE
: uPROG TRACE PD, PE ENABLE
OUTPUTS
DA0 - DA11 : DRAM ADDRESS
DLCAS
: DRAM CAS, LOWER
DRAS0 DRAS3
-
: DRAM RAS0 - RAS3
DUCAS
: DRAM CAS, UPPER
DWE
: DRAM WRITE ENABLE
ICLK : I/O CLOCK PROGRAMMABLE FREQ.
IDACK0 IDACK3
-
: DMA ACKNOWLEDGE, CH0 - CH3
ILDOUT
: LOAD OUTPUT, WRITE TO I/O PORT
ILIOA
: LOAD I/O ADDRESS TO I/O PORT
INEXT
: NEXT INPUT, READ FROM I/O PORT
MCKOUT : REFERENCE CLOCK 33 MHz
MEXEC
: PROCESSOR CYCLE CLOCK
MIRQOUT
: INTERRUPT FOR SWITCH DEBUG
MRES2 : RTC XTAL 32.768 kHz
MRSTOUT
: GLOBAL RESET, DELAYED
MSDOUT : SERIAL DATA FOR SWITCH DEBUG
MX2
: XTAL 16.67/33 MHz
T_VCOV : TEST (CONTROL VOLTAGE OF VCO)
TDA_PE0 - PDA_PE7
: PORT PE
TYA_PD0 - TYA_PD7
: PORT PD
INPUTS/OUTPUTS
DD0 - DD15 : DRAM DATA
ID0 - ID7
: DMA DATA BUS
PA0 - PA7
: PORT PA
PB0 - PB7 : PORT PB
PC0 - PC7
: PORT PC
OTHERS
A.GND
: ANALOG GROUND
R.GND : GROUND
V
CCA : ANALOG SUPPLY VOLTAGE
V : RTC SUPPLY
CCR
PIN
SIGNAL I/O SIGNAL
NO.
I/O
DA2 97 PA2
I/O
DA1 98 PA1
I/O
DA0 99 PA0
GND 100 — GND
—
V 101 V
CC CC
MRSTOUT
O
DD15 102
I
DD14 103 TENABLE
I/O
DD13 104 ID7
DD12 105 I/O ID6
I/O
DD11 106 ID5
DD10 107 I/O ID4
I/O
DD9 108 GND
—
DD8 109 V
CC
I/O
GND 110 ID3
I/O
V 111 ID2
CC
DD7 112 I/O ID1
I/O
DD6 113 ID0
IDACK3
O
DD5 114
IDACK2
O
DD4 115
IDACK1
O
DD3 116
IDACK0
DD2 117 O
IDREQ3
I
DD1 118
IDREQ2
DD0 119 I
—
GND 120 GND
—
V 121 V
CC CC
IDREQ1
I
PC7 122
IDREQ0
I
PC6 123
PC5 124 O ICLK
ILIOA
O
PC4 125
ILDOUT
O
PC3 126
INEXT
O
PC2 127
MIRQ1
I
PC1 128
MIRQ0
PC0 129 I
—
PB7 130 GND
PB6 131 — V
CC
O
PB5 132 MEXEC
MIRQOUT
O
PB4 133
O
PB3 134 MCKOUT
I
PB2 135 CLK_SEL
PB1 136 I T_EN
O
PB0 137 T_VCOV
I
GND 138 T_VCOM
—
V 139 A.GND
CC
O
PA7 140 MX2
PA6 141 I MX1_CK
—
PA5 142 V
CCA
MRESET
PA4 143 I
—
PA3 144 GND
UCP-8060