Abit AN8 32X User Manual page 42

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RAS# Precharge Time:
This item specifies the RAS# precharge time.
RAS# to RAS# Delay:
This item specifies the RAS# active to RAS# active delay time of different bank.
Write Recovery Time:
This item specifies the time measured from the last write datum is safely registered by the DRAM.
Write to Read Delay:
This item specifies the time measured from the rising edge following the last non-masked data strobe to
the rising edge of the next read command.
Read to Write Delay:
This item specifies the read to write delay.
DRAM Command Rate:
When the host (northbridge) locates the desired memory address, it then processes the wait state of
commands.
Bank Interleaving:
Depending on your SDRAM module structure, the 4-Way setting can offer the best performance. If you
choose the wrong setting, the computer system will not run in a stable manner. For detailed information
on your SDRAM module, please ask your SDRAM module manufacturer.
Burst Length
DDR SDRAM modules provide a Burst mode that means an auto precharge function for programmable
READ or WRITE burst lengths of 2, 4 or 8 locations.
This means that if we set burst length to 8, the address bus will access 8 bytes each cycle to precharge,
etc.
MTRR mapping mode
The item selects the MTRR mapping mode. The MTRR (Memory-Type and Range Registers) controls
the access and cacheability of memory regions in the processor.
32 bit Dram Memory Hole:
This item selects the method to remap the 32 bit Dram memory hole. Leave this item to its default "Auto"
Setting.
Back to Advanced Chipset Features Setup Menu:
SSE/SSE2 Instructions:
This item allows you to Enable or Disable the SSE/SSE2 (Streaming SIMD Extensions) instruction set.
The default setting is Enabled.
System BIOS Cacheable:
Two options are available: Disabled or Enabled. When you select Enabled, you get faster system BIOS
executing speed via the L2 cache.
AN8 32X
Chapter 3