Dram Configuration - Abit AN8 32X User Manual

BIOS Setup

DRAM Configuration:

Click <Enter> key to enter its submenu:
DRAM Timing Selectable
X - DRAM Clock
X - CAS Latency Time
X - Row Cycle Time
X - Row Refresh Cycle Time
X - Min RAS# Active Time
X - RAS# to CAS# Delay
X - RAS# Precharge Time
X - RAS# to RAS# Delay
X - Write Recovery Time
X - Write to Read Delay
X - Read to Write Delay
X - DRAM Command Rate
X - Bank Interleaving
X - Burst Length
MTRR mapping mode
32 bit Dram Memory Hole
↑↓→←:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
DRAM Timing Selectable:
This item selects the DRAM timing mode. When set to "By SPD", the BIOS will read the DRAM module
SPD data and automatically set to the values stored in it. Leave this item to its default "Auto" setting.
DRAM Clock:
This item sets the DRAM clock of your DRAM module. The system may be unstable or unable to boot up
if your DRAM module does not support the clock you set.
When set to [By SPD], the BIOS will read the DRAM module SPD data and automatically set the DRAM
clock by the value stored in it.
CAS Latency Time:
You can select SDRAM CAS (Column Address Strobe) latency time according your SDRAM
specification.
Row Cycle Time:
This item specifies the RAS# active to RAS# active time or auto refresh time of the same bank.
Row Refresh Cycle Time:
This item specifies the auto refresh active to RAS# active time or RAS# auto refresh time.
Min. RAS# Active Time:
This item specifies the minimum RAS# active time.
RAS# to CAS# Delay:
This item specifies the RAS# active to CAS# read write delay time to the same bank.
Phoenix – Award BIOS CMOS Setup Utility
DRAM Configuration
F6: Fail-Safe Defaults
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Enabled
4 beats
Continuous
Auto
Item Help
F7: Optimized Defaults
3-15
User's Manual