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LPC connector
The Low Pin Count Interface was defi ned by Intel
dustry's transition towards legacy free systems. It allows the integration of low-
bandwidth legacy I/O components within the system, which are typically provided
by a Super I/O controller. Furthermore, it can be used to interface fi rmware hubs,
Trusted Platform Module (TPM) devices and embedded controller solutions. Data
transfer on the LPC bus is implemented over a 4 bit serialized data interface, which
uses a 33MHz LPC bus clock. For more information about LPC bus refer to the Intel
Low Pin Count Interface Specifi cation Revision 1.1'.
Hardware Installation
1
2
CLK
LAD1
RST#
LAD0
VCC3
FRAME#
GND
LAD3
LAD2
9
Corporation to facilitate the in-
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2
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