6.2.2.1 Write DRQ Interval Time
For write sectors and write multiple operations, 4.8 sec is inserted from the end of negation of the D R Q bit
until setting of the next D R Q bit.
6.2.2.2 Read DRQ Interval Time
For read sectors and read multiple operations, the interval from the end of negation of the D R Q bit until
setting of the next D R Q bit is as follows;
In case that a host reads the status register only before the sector or block transfer D R Q interval
D R Q interval ............ 5.2 sec.
In case that a host reads the status register after or both before and after the sector or block transfer
D R Q interval ............ 14.4 sec.
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O E M Specifications for DTTA-3xxxxx