IBM DTTA-351010 - Deskstar 10.1 GB Hard Drive Specifications
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IBM DTTA-351010 - Deskstar 10.1 GB Hard Drive Specifications

IBM DTTA-351010 - Deskstar 10.1 GB Hard Drive Specifications

Dtta-3 series (16.8gb - 3.2gb) 3.5-inch hard disk drive with ata interface
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See also: Installation Manual
S00K-0286-02
OEM HARD DISK DRIVE SPECIFICATIONS
for
DTTA-3xxxxx ( 16.8GB - 3.2GB )
3.5-Inch Hard Disk Drive with ATA Interface
Revision (2.0)

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Summary of Contents for IBM DTTA-351010 - Deskstar 10.1 GB Hard Drive

  • Page 1 S00K-0286-02 OEM HARD DISK DRIVE SPECIFICATIONS DTTA-3xxxxx ( 16.8GB - 3.2GB ) 3.5-Inch Hard Disk Drive with ATA Interface Revision (2.0)
  • Page 3 S00K-0286-02 OEM HARD DISK DRIVE SPECIFICATIONS DTTA-3xxxxx ( 16.8GB - 3.2GB ) 3.5-Inch Hard Disk Drive with ATA Interface Revision (2.0)
  • Page 4 This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. IBM may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time.

  • Page 5: Table Of Contents

    ........Copyright IBM Corp. 1998...
  • Page 6 6.6.3 Data Reliability ..........6.6.4 Cable Noise Interference .
  • Page 7 10.0 General Operation Descriptions ........10.1 Reset Response .
  • Page 8 12.16 Read Sectors (20h/21h) ......... . 12.17 Read Verify Sectors (40h/41h) .

  • Page 9: General

    1.0 General This document describes the specifications of the following IBM 3.5-inch, ATA interface hard disk drives: DTTA-351680 ( 16.8 GB ) ( 5400 rpm ) DTTA-351350 ( 13.5 GB ) ( 5400 rpm ) DTTA-351290 ( 12.9 GB ) ( 5400 rpm ) DTTA-351010 ( 10.1 GB ) ( 5400 rpm )
  • Page 10 O E M Specifications for DTTA-3xxxxx...

  • Page 11: General Features

    Ultra DMA/33 (33.3 MB/sec) CHS and LBA mode Transparent Defect Management with A D R (Automatic Defect Reallocation) Power Saving modes S.M.A.R.T. function support Seculity function support Default Logical Head Number (16 or 15) selectable with jumper Copyright IBM Corp. 1998...
  • Page 12 O E M Specifications for DTTA-3xxxxx...

  • Page 13: Part 1. Functional Specification

    Part 1. Functional Specification Copyright IBM Corp. 1998...
  • Page 14 O E M Specifications for DTTA-3xxxxx...

  • Page 15: Drive Characteristics

    The values with * in column of Word 3 (Head) of the above list indicate Ship Default. The default value of Word 3 (Head) can be changed by jumper. For jumper setting, refer to 6.3, “Jumper Settings” on page 38. Copyright IBM Corp. 1998...

  • Page 16: Data Sheet

    3.2 Data Sheet DTTA-35xxxx DTTA-37xxxx Media Transfer Rate (Mb/sec) 92.2 - 163.7 111.6 - 175.6 Interface Transfer Rate (MB/sec) 16.6 (PIO Mode-4) 16.6 (PIO Mode-4) 33.3 (Ultra DMA/33) 33.3 (Ultra DMA/33) Data Buffer Size (KB) Rotational Speed (RPM) 5400 7200 Average Latency (msec) 5.56 4.17...

  • Page 17: Performance Characteristics

    3.3 Performance Characteristics A file performance is characterized by the following parameters: Command Overhead Mechanical Positioning Seek Time Latency Data Transfer Speed Buffering Operation (Look ahead/Write cache) Note: All the above parameters contribute to file performance. There are other parameters that contribute to the performance of the actual system.
  • Page 18 Maximum value measured on any one drive over the full range of the environmental and voltage conditions. (See section on Environment and D.C. Power Requirement.) The seek time is measured from the start of motion of the actuator until a reliable read or write operation may be started.

  • Page 19: Drive Ready Time

    3.3.2.4 Cylinder Switch Time (Cylinder Skew) DTTA-35xxxx DTTA-37xxxx Cylinder Switch Time (Typical) 3.4 msec 2.6 msec Figure 7. Cylinder Switch Time A cylinder switch time is defined as the amount of time required by the fixed disk to complete seek the next sequential block after reading the last track in the current cylinder.

  • Page 20: Data Transfer Speed

    3.3.4 Data Transfer Speed Description DTTA-35xxxx DTTA-37xxxx Disk-Buffer Transfer (Zone 0) Instantaneous - typical 15.2 Mbyte/sec 16.2 Mbyte/sec Sustained - typical 12 Mbyte/sec 13 Mbyte/sec Disk-Buffer Transfer (Zone 7) Instantaneous - typical 8.3 Mbyte/sec 10.1 Mbyte/sec Sustained - typical 6 Mbyte/sec 8 Mbyte/sec Buffer-Host (max)

  • Page 21: Throughput

    3.3.5 Throughput 3.3.5.1 Simple Sequential Access Operation DTTA-35xxxx DTTA-37xxxx typical / max. typical / max. Sequential Read (Zone 0) 1.4 sec / 1.5 sec 1.3 sec / 1.4 sec Sequential Read (Zone 7) 2.6 sec / 2.7 sec 2.2 sec / 2.3 sec Figure 12.

  • Page 22: Operating Mode Definition

    3.3.6 Operating Mode Definition Operating Mode Description Spin-Up Start up time period from spindle stop or power down. Seek Seek operation mode Write Write operation mode Read Read operation mode Idle Spindle motor and servo system are working normally. Commands can be received and processed immediately. Standby Spindle motor is stopped.

  • Page 23: Data Integrity

    Appropriate error status is made available to the host system if any of the following conditions occur after the drive has once become ready: Spindle speed outside requirements for reliable operation. Occurrence of a WRITE FAULT condition. Copyright IBM Corp. 1998...
  • Page 24 O E M Specifications for DTTA-3xxxxx...

  • Page 25: Physical Format

    | Note: There is possibility to reallocate sectors during drive usage including early period. It is mainly caused | by handling problem, and the reallocation is normal maintenance work of Hard Disk Drive. Copyright IBM Corp. 1998...
  • Page 26 O E M Specifications for DTTA-3xxxxx...

  • Page 27: Specification

    (part 61173-4) loose piece, or their equivalents. Pin assignments are shown below. Voltage + 12 V G N D G N D + 5 V Figure 14. Power Connector Pin Assignments 6.1.1.2 AT Signal Connector The AT signal connector is a 40-pin connector. Copyright IBM Corp. 1998...

  • Page 28: Signal Definition

    6.1.2 Signal Definition The pin assignments of interface signals are listed as follows: P I N S I G N A L I / O T y p e P I N S I G N A L I / O T y p e R E S E T T T L...
  • Page 29 DD00-DD15 16-bit bi-directional data bus between the host and the HDD. The lower 8 lines, DD00-07, are used for Register and ECC access. All 16 lines, DD00-15, are used for data transfer. These are 3-State lines with 24 mA current sink capability. DA00-DA02 Address used to select the individual register in the HDD.
  • Page 30 00h. Device 0 may be unable to accept commands until it has finished its reset procedure and is ready ( D R D Y = 1 ) . CSEL (Cable Select) (Optional) The drive is configured as either Device 0 or 1 depending upon the value of CSEL. If CSEL is grounded then the device address is 0.

  • Page 31: Interface Logic Signal Levels

    DSTROBE (Ultra DMA) This signal is used only for Ultra D M A data transfers between host and drive. DSTROBE is the data int strobe signal from the device for an Ultra D M A data in transfer. Both the rising and falling edge of DSTROBE latch the data from DD(15:0) into the host. The device may stop toggling DSTROBE to pause an Ultra D M A data in transfer.

  • Page 32: Signal Timings

    6.2 Signal Timings 6.2.1 Reset Timings H D D reset timing. R E S E T < > B U S Y X X X X X X X < > P A R A M E T E R D E S C R I P T I O N M i n M a x ( u s e c ) ( s e c )

  • Page 33: Pio Timings

    6.2.2 PIO Timings The PIO cycle timings meet Mode 4 of the ATA-3 description. C S 0 , C S 1 + D A 0 2 < > < T 1 > < > D I O R , D I O W <...

  • Page 34: Write Drq Interval Time

    6.2.2.1 Write DRQ Interval Time For write sectors and write multiple operations, 4.8 sec is inserted from the end of negation of the D R Q bit until setting of the next D R Q bit. 6.2.2.2 Read DRQ Interval Time For read sectors and read multiple operations, the interval from the end of negation of the D R Q bit until setting of the next D R Q bit is as follows;...

  • Page 35: Dma Timings

    6.2.3 DMA Timings 6.2.3.1 Single Word DMA Timings The Single Word D M A timing meets Mode 2 of the ATA-2 description. < > + D M A R Q < > D M A C K > T I < >...

  • Page 36: Multiword Dma Timings

    6.2.3.2 Multiword DMA Timings The Multiword D M A timing meets Mode 2 of the ATA-4 description. < T L > D M A R Q > T J < D M A C K < > > T I < >...

  • Page 37: Ultra Dma Timings

    6.2.4 Ultra DMA Timings The Ultra D M A timing meets Mode 0, 1 and 2 of the Ultra DMA/33 -- a Proposal for a New Protocol in ATA/ATAPI-4 (X3T13/1153D Revision 16) 6.2.4.1 Initiating Read DMA D M A R Q <...

  • Page 38: Host Pausing Read Dma

    6.2.4.2 Host Pausing Read DMA D M A R Q D M A C K S T O P < T s r > H D M A R D Y < T r f s > D S T R O B E [ n s e c ] M O D E 0 M O D E 1...

  • Page 39: Host Terminating Read Dma

    6.2.4.3 Host Terminating Read DMA < T l i > D M A R Q < T m l i > D M A C K < T r p > < T a c k > S T O P <...

  • Page 40: Device Terminating Read Dma

    6.2.4.4 Device Terminating Read DMA < > T s s D M A R Q < T m l i > D M A C K < T l i > < T a c k > S T O P <...

  • Page 41: Initiating Write Dma

    6.2.4.5 Initiating Write DMA D M A R Q < T u i > D M A C K < T a c k > < T e n v > S T O P T z r d y > <...

  • Page 42: Device Pausing Write Dma

    6.2.4.6 Device Pausing Write DMA D M A R Q D M A C K S T O P < T s r > D D M A R D Y < T r f s > H S T R O B E [ n s e c ] M O D E 0 M O D E 1...

  • Page 43: Device Terminating Write Dma

    6.2.4.7 Device Terminating Write DMA < T r p > D M A R Q < T m l i > D M A C K < T a c k > S T O P < > T r d y z D D M A R D Y <...

  • Page 44: Host Terminating Write Dma

    6.2.4.8 Host Terminating Write DMA < T l i > D M A R Q < T m l i > D M A C K < > T s s < T a c k > S T O P <...

  • Page 45: Addressing Of Hdd Registers

    6.2.5 Addressing of HDD Registers The host addresses the drive through a set of registers called the Task File. These registers are mapped into the host's I/O space. Two chip select lines (-CS0 and -CS1) and three address lines (DA00-02) are used to select one of these registers, while a -DIOR or -DIOW is provided at the specified time.

  • Page 46: Jumper Settings

    6.3 Jumper Settings 6.3.1 Location of Jumper Pin Jumper pins are located between power pins and AT interface pins. Refer to 6.7.3, “ Connector Locations” on page 51 for location of the jumper pins. Pin position A is indi- cated in the figure. 6.3.2 Jumper Pin Assignment Pin number A through I are prepared for jumper setting.

  • Page 47: Jumper Set Position

    6.3.4 Jumper Set Position 6.3.4.1 For Default Logical Head 16 D E V I C E 0 < S h i p p i n g D e f a u l t e x c e p t D T T A 3 5 0 6 4 0 / 3 5 0 4 3 0 D E V I C E 1 C A B L E S E L E C T D E V I C E 0...
  • Page 48 6.3.4.2 For Default Logical Head 15 D E V I C E 0 < S h i p p i n g D e f a u l t f o r D T T A 3 5 0 6 4 0 / 3 5 0 4 3 0 D E V I C E 1 C A B L E S E L E C T D E V I C E 0...
  • Page 49 6.3.4.3 For Capacity Clip to 2GB with Default Logical Head 16 D E V I C E 0 D E V I C E 1 C A B L E S E L E C T D E V I C E 0 F o r c i n g D E V I C E 1 P R E S E N T Figure 33.
  • Page 50 6.3.4.4 For Disabling Auto Spin with Default Logical Head 16 D E V I C E 0 D E V I C E 1 C A B L E S E L E C T D E V I C E 0 F o r c i n g D E V I C E 1 P R E S E N T Figure 34.

  • Page 51: Environment

    6.4 Environment Figure 35. Environmental Condition Operating Conditions Temperature 5 to 55˚ C (See note) Relative Humidity 8 to 90 % R H non-condensing Maximum Wet Bulb Temperature 29.4˚ C non-condensing Maximum Temperature Gradient 15˚ C / Hour Altitude 300 to 3048 m Non-Operating Conditions Temperature 40 to 65˚...

  • Page 52: Dc Power Requirements

    6.5 DC Power Requirements Connection to the product should be made in isolated secondary circuits (SELV). The following voltage specification is applied at the power connector of the drive. Damage to the file electronics may result if the power supply cable is connected or disconnected while power is being applied to the file (Hot plug/unplug is not allowed).
  • Page 53 Figure 39. Power Supply Current of DTTA-351010/350840/350640/350430/350320 +5Volts +12Volts Total (All values in Amps.) Pop Mean Std.Dev Pop Mean Std.Dev Idle Average 0.29 0.02 0.16 0.05 Idle ripple (peak-to-peak) 0.22 0.04 Seek peak 0.02 1.23 Seek average (*1) 0.33 0.02 0.37 Start up (max) 0.02...

  • Page 54: Start Up Current

    6.5.1 Start Up Current 6.5.1.1 DTTA-351010/350840/350640/350430/350320 Figure 41. Typical Current Wave Form of 12V at Start Up of DTTA-351010/350840/350640/350430/350320. 6.5.1.2 DTTA-351680/351350/351290 Figure 42. Typical Current Wave Form of 12V at Start Up of DTTA-351680/351350/351290. O E M Specifications for DTTA-3xxxxx...
  • Page 55 6.5.1.3 DTTA-371440/371290/371010 Figure 43. Typical Current Wave Form of 12V at Start Up of DTTA-371440/371290/371010. Specification...

  • Page 56: Reliability

    6.6 Reliability 6.6.1 Contact Start Stop (CSS) The drive is designed to withstand a minimum of 40,000 contact start/stop cycles at 40˚ C with 13-25% rela- tive humidity. The drive is designed to withstand a minimum of 10,000 contact start/stop cycles at operating environment conditions specified in 6.4, “...

  • Page 57: Mechanical Specifications

    6.7 Mechanical Specifications 6.7.1 Outline Figure 44. Outline of DTTA-3xxxxx 6.7.2 Mechanical Dimensions and Weight The following chart describes the dimensions for the 3.5" hard disk drive form factor. DTTA-371440 DTTA-351680 DTTA-351010 DTTA-371290 DTTA-351350 DTTA-350840 DTTA-371010 DTTA-351290 DTTA-350640 DTTA-350430 DTTA-350320 Height (mm) 25.4 ±...
  • Page 58 Figure 46. Mechanical Dimension O E M Specifications for DTTA-3xxxxx...

  • Page 59: Connector Locations

    6.7.3 Connector Locations Figure 47. Connector Locations Specification...

  • Page 60: Hole Locations

    6.7.4 Hole Locations The Figure 48 on page 52 shows the outline of DTTA-3xxxxx which includes the hole locations. Figure 48. Mounting Positions and the Tappings O E M Specifications for DTTA-3xxxxx...

  • Page 61: Mounting Orientation

    6.7.5 Mounting Orientation The drive will operate in all axes (6 directions). The drive will operate within the specified error rates when tilted ± 5 degree from these positions. Performance and error rate will stay within specification limits if the drive is operated in the other permis- sible orientations from which it was formatted.

  • Page 62: Vibration And Shock

    6.8 Vibration and Shock All vibration and shock measurements in this section are made with the drive that has no mounting attach- ments for the systems. The input power for the measurements is applied to the normal drive mounting points. 6.8.1 Operating Vibration 6.8.1.1 Random Vibration The drive is designed to operate without unrecoverable errors while being subjected to the following...

  • Page 63: Non-Operating Vibrations

    6.8.2 Non-Operating Vibrations The drive does not sustain permanent damage or loss of recorded data after being subjected to the environ- ment described below. 6.8.2.1 Random Vibration The test consists of a random vibration applied for each of three mutually perpendicular axes with the time duration of 10 minutes per axis.

  • Page 64: Acoustics

    6.9 Acoustics The following shows the acoustic levels. 6.9.1 Sound Power Levels The upper limit criteria of the A-weighted sound power levels are given in Bel relative to one pico watt and are shown in the following table. The measurment method is in accodance with ISO7779. Figure 51.

  • Page 65: Sound Pressure (Reference)

    6.9.2 Sound Pressure (Reference) 6.9.2.1 Unit Sound Pressure Level Measurment The hard disk drives are measured in a semi-anechoic chamber, with background noise = < 25 dBA. Sur- faces to be measured are top cover side and card side. Microphone is set one meter above the drive surface. Random operation mode is simulated with 40% seek and 60% idle in time.

  • Page 66: Identification

    The following labels are affixed to every disk drive . A label containing IBM logo, IBM part number and the statement 'Made by IBM' or equivalent. A label containing drive model number, date code, formatted capacity, place of manufacture, and UL/CSA/TUV/CE/C-Tick mark logos.

  • Page 67: Safety

    6.12 Safety 6.12.1 Underwriters Lab(UL) Approval DTTA-3xxxxx complies with UL 1950. 6.12.2 Canadian Standards Authority(CSA) Approval DTTA-3xxxxx complies with CAN/CSA-22.2 No.0M91 and No.950-93. 6.12.3 IEC Compliance DTTA-3xxxxx complies with IEC 950. 6.12.4 German Safety Mark DTTA-3xxxxx are approved by TUV on Test Requirement: EN 60 950:1988/A1:1990/A2:1991.
  • Page 68 O E M Specifications for DTTA-3xxxxx...

  • Page 69: Part 2. Ata Interface Specification

    Part 2. ATA Interface Specification Copyright IBM Corp. 1998...
  • Page 70 O E M Specifications for DTTA-3xxxxx...

  • Page 71: General

    Interface Extension (ATA/ATAPI-4) Revision 17 dated on 30 October 1997 with certain limitations described in 8.0, “Deviations From Standard” on page 65. 7.2 Terminology Device Device indicates DTTA-3xxxxx. Host Host indicates the system that the device is attached to. Copyright IBM Corp. 1998...
  • Page 72 O E M Specifications for DTTA-3xxxxx...

  • Page 73: Deviations From Standard

    Idle mode. This command does not support 80h as the return value. Hard Reset Hard reset response is not the same as that of power on reset. Refer to section 10.1, “Reset Response” on page 73 for detail. Copyright IBM Corp. 1998...
  • Page 74 O E M Specifications for DTTA-3xxxxx...

  • Page 75: Registers

    The Command Block Registers are used for sending commands to the device or posting status from the device. The Control Block Registers are used for device control and to post alternate status. 9.1 Alternate Status Register Copyright IBM Corp. 1998...

  • Page 76: Command Register

    A l t e r n a t e S t a t u s R e g i s t e r B S Y R D Y D S C D R Q C O R I D X E R R / S E R V Figure 56.

  • Page 77: Device Control Register

    The register contains valid data only when D R Q = 1 in the Status Register. 9.6 Device Control Register D e v i c e C o n t r o l R e g i s t e r S R S T I E N Figure 57.

  • Page 78: Error Register

    D e v i c e / H e a d R e g i s t e r D R V H S 3 H S 2 H S 1 H S 0 Figure 59. Device/Head Register This register contains the device and head numbers. Bit Definitions Binary encoded address mode select.

  • Page 79: Features Register

    TK0NF (T0N) Track 0 Not Found. T 0 N = 1 indicates track 0 was not found during a Recalibrate command. AMNF (AMN) Address Mark Not Found. A M N = 1 indicates the data address mark has not been found after finding the correct ID field for the requested sector.

  • Page 80: O E M Specifications For Dtta-3Xxxxx

    The use of bit 4 is command dependent. After the D M A Queued commands, it is used as SERV. After any other commands or reset, it is used as DSC. Bit Definitions Busy. B S Y = 1 whenever the device is accessing the registers. The host should not read or write any registers when B S Y = 1 .

  • Page 81: General Operation Descriptions

    Default value on P O R is shown in Figure 63 on page 74. (*3) The Set Features command with Feature register = CCh enables the device to revert these parameters to the power on defaults. Copyright IBM Corp. 1998...

  • Page 82: Register Initialization

    (*4) In the case of Sleep mode, the device goes to Standby mode. In other case, the device does not change current mode. 10.1.1 Register Initialization R e g i s t e r D e f a u l t V a l u e E r r o r D i a g n o s t i c C o d e S e c t o r C o u n t...

  • Page 83: Sector Addressing Mode

    the BSY bit whenever it is ready to accept commands. Device 0 may assert DASP- to indicate device activity. Hard Reset, Soft Reset If Device 1 is present Device 0 shall read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors, otherwise Device 0 shall simply reset and clear the BSY bit.

  • Page 84: Logical Chs Addressing Mode

    10.3.1 Logical CHS Addressing Mode The logical CHS addressing is made up of three fields: the cylinder number, the head number and the sector number. Sectors are numbered from 1 to the maximum value allowed by the current CHS translation mode but can not exceed 255(0FFh).

  • Page 85: Power Management Feature

    For the READ D M A QUEUED and WRITE D M A QUEUED commands, the device may or may not perform a bus release. If the device is ready to complete execution of the command, it may complete the command immediately. If the device is not ready to complete execution of the command, the device may perform a bus release and complete the command via a service request.

  • Page 86: Power Mode

    2. Idle command 3. Idle Immediate command 4. Sleep command 5. Standby command 6. Standby Immediate command 10.5.1 Power Mode The lowest power consumption when the device is powered on occurs in Sleep Mode. When in sleep mode, the device requires a reset to be activated. In Standby Mode the device interface is capable of accepting commands, but as the media may not imme- diately accessible, there is a delay while waiting for the spindle to reach operating speed.

  • Page 87: Function

    M o d e B S Y R D Y I n t e r f a c e a c t i v e M e d i a A c t i v e Y e s A c t i v e I d l e Y e s A c t i v e...

  • Page 88: Commands

    10.6.5 S.M.A.R.T. commands The S.M.A.R.T. commands provide access to attribute values, attribute thresholds and other logging and reporting information. 10.7 Security Mode Feature Set Security Mode Feature Set is a powerful security feature. With a device lock password, a user can prevent unauthorized access to hard disk device even if the device is removed from the computer.

  • Page 89: Operation Example

    Master Password When the Master Password is set, the device does N O T enable the Device Lock Function, and the device can N O T be locked with the Master Password, but the Master Password can be used for unlocking the device locked. User Password The User Password should be given or changed by a system user.
  • Page 90 10.7.4.3 Operation from POR after User Password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed. P O R > D e v i c e L o c k e d m o d e <...

  • Page 91: User Password Lost

    10.7.4.4 User Password Lost If the User Password is forgotten and High level security is set, the system user can't access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.

  • Page 92: Command Table

    10.7.5 Command Table This table shows the device's response to commands when the Security Mode Feature Set (Device lock func- tion) is enabled. Command Locked Mode Unlocked Mode Frozen Mode Check Power Mode Executable Executable Executable Execute Device Diagnostic Executable Executable Executable Flush Cache...
  • Page 93 Command Locked Mode Unlocked Mode Frozen Mode SMART Save Attribute Values Executable Executable Executable Standby Executable Executable Executable Standby Immediate Executable Executable Executable Write Buffer Executable Executable Executable Write D M A (w/o retry) Command aborted Executable Executable Write D M A (w/retry) Command aborted Executable Executable...

  • Page 94: Protected Area Function

    10.8 Protected Area Function Protected Area Function is to provide the 'protected area' which can not be accessed via conventional method. This 'protected area' is used to contain critical system data such as BIOS or system management information. The contents of entire system main memory may also be dumped into 'protected area' to resume after system power off.

  • Page 95: Write Cache Function

    From this point, the protected area cannot be accessed till next Set Max LBA/CYL command is issued. Any BIOSes, device drivers, or application software access the H D D as if that is the 6.2GB device because the device acts exactly same as real 6.2GB device does. 3.

  • Page 96: Auto Reassign Function

    10.10.1 Auto Reassign Function The sectors those show some errors may be reallocated automatically when specific conditions are met. The spare sectors for reallocation are located at the end of drive. The conditions for auto-reallocation are described below. Non recovered write errors When a write operation can not be completed after the Error Recovery Procedure(ERP) is fully carried out, the sector(s) are reallocated to the spare location.

  • Page 97: Command Protocol

    In response to the interrupt, the host reads the Status Register. d. The device clears the interrupt in response to the Status Register being read. e. The host reads one sector (or block) of data via the Data Register. Copyright IBM Corp. 1998...

  • Page 98: Pio Data Out Commands

    f. The device sets D R Q = 0 after the sector (or block)has been transferred to the host. 4. For the Read Long command: a. The device sets B S Y = 1 and prepares for data transfer. b. When the sector of data is available for transfer to the host, the device sets B S Y = 0 , sets D R Q = 1 , and interrupts the host.

  • Page 99: Non-Data Commands

    Write Sectors Execution includes the transfer of one or more 512 byte ( > 5 1 2 bytes on Write Long) sectors of data from the host to the device. 1. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head Registers.

  • Page 100: Dma Commands

    Idle Idle Immediate Initialize Device Parameters N O P Read Native Max LBA/CYL Read Verify Sectors Recalibrate Security Erase Prepare Security Freeze Lock Seek Set Features Set Max LBA/CYL Set Multiple Mode Sleep SMART Disable Operations SMART Enable/Disable Attribute Autosave SMART Enable Operations SMART Execute Off-line Data Collection SMART Return Status...

  • Page 101: Dma Queued Commands

    data transfers are performed using the slave-DMA channel no intermediate sector interrupts are issued on multi-sector commands Initiation of the D M A transfer commands is identical to the Read Sector or Write Sector commands except that the host initializes the slave-DMA channel prior to issuing the command. The interrupt handler for D M A transfers is different in that: no intermediate sector interrupts are issued on multi-sector commands the host resets the D M A channel prior to reading status from the device.
  • Page 102 c. The host may issue another command or wait for service request from the device. 3. Bus Release If the device is not ready for data transfer (REL is set), a. The device generates an interrupt if release interrupt is enabled. b.

  • Page 103: Command Descriptions

    S e t M a x L B A / C Y L 1 1 1 1 1 0 0 1 S e t M u l t i p l e M o d e 1 1 0 0 0 1 1 0 Figure 71. Command Set Copyright IBM Corp. 1998...
  • Page 104 P r o t o C o m m a n d C o d e B i n a r y C o d e c o l ( H e x ) B i t 7 6 5 4 3 2 1 0 S l e e p 1 1 1 0 0 1 1 0 S l e e p *...
  • Page 105 C o m m a n d F e a t u r e C o m m a n d ( S u b c o m m a n d ) C o d e R e g i s t e r ( H e x ) ( H e x ) ( S .
  • Page 106 The following symbols are used in the command descriptions: Output Registers Indicates that the bit must be set to 0. Indicates that the bit must be set to 1. The device number bit. Indicates that the device number bit of the Device/Head Register should be specified.

  • Page 107: Check Power Mode (E5H/98H)

    12.1 Check Power Mode (E5h/98h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 108: Execute Device Diagnostic (90H)

    12.2 Execute Device Diagnostic (90h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 109: Flush Cache (E7H)

    12.3 Flush Cache (E7h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 110: Format Track (50H)

    12.4 Format Track (50h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 111 Input Parameters From The Device Sector Number In LBA mode, this register specifies current LBA address bits 0-7. ( L = 1 ) Cylinder High/Low In LBA mode, this register specifies current LBA address bits 8-15 (Low), 16-23 (High) In LBA mode, this register specifies current LBA address bits 24-27. ( L = 1 ) Error The Error Register.

  • Page 112: Identify Device (Ech)

    12.5 Identify Device (ECh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 113 W o r d C o n t e n t D e s c r i p t i o n 0 4 5 A H D r i v e c l a s s i f i c a t i o n , b i t a s s i g n m e n t s : 1 5 ( = 0 ) : 1 = A T A P I d e v i c e , 0 = A T A d e v i c e 1 4 ( = 0 ) : 1 = f o r m a t s p e e d t o l e r a n c e g a p r e q u i r e d 1 3 ( = 0 ) : 1 = t r a c k o f f s e t o p t i o n a v a i l a b l e...
  • Page 114 W o r d C o n t e n t D e s c r i p t i o n x F 0 0 H C a p a b i l i t i e s , b i t a s s i g n m e n t s : 1 5 1 4 ( = 0 ) R e s e r v e d S t a n d b y t i m e r ( = 1 )
  • Page 115 W o r d C o n t e n t D e s c r i p t i o n 0 0 7 8 H M a n u f a c t u r e r ' s R e c o m m e n d e d M u l t i w o r d D M A T r a n s f e r C y c l e T i m e 0 ( = 7 8 ) C y c l e t i m e i n n a n o s e c o n d s ( 1 2 0 n s , 1 6 .
  • Page 116 W o r d C o n t e n t D e s c r i p t i o n x x x x H C o m m a n d s e t / f e a t u r e e n e b l e d R e s e r v e d N O P c o m m a n d R E A D B U F F E R c o m m a n d...
  • Page 117 W o r d C o n t e n t D e s c r i p t i o n 1 2 8 x x x x H D e v i c e L o c k F u n c t i o n . B i t a s s i g n m e n t s 9 R e s e r v e d 8 S e c u r i t y L e v e l 1 = M a x i m u m , 0 = H i g h...

  • Page 118: Idle (E3H/97H)

    12.6 Idle (E3h/97h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 119 When the automatic power down sequence is enabled, the drive will enter Standby mode automatically if the timeout interval expires with no drive access from the host. The timeout interval will be reinitialized if there is a drive access before the timeout interval expires.

  • Page 120: Idle Immediate (E1H/95H)

    12.7 Idle Immediate (E1h/95h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 121: Initialize Device Parameters (91H)

    12.8 Initialize Device Parameters (91h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 122: Nop (00H)

    12.9 NOP (00h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 123: Read Buffer (E4H)

    12.10 Read Buffer (E4h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 124: Read Dma (C8H/C9H)

    12.11 Read DMA (C8h/C9h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 125 The head number of the first sector to be transferred. ( L = 0 ) In LBA mode, this register specifies LBA bits 24-27 to be transferred. ( L = 1 ) The retry bit. If set to one, then retries are disabled. Input Parameters From The Device Sector Count The number of requested sectors not transferred.

  • Page 126: Read Dma Queued (C7H)

    12.12 Read DMA Queued (C7h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 127 Input Parameters From The Device On Bus Release Sector Count bits 7 - 3 (Tag) contain the Tag of the command being bus released. bit 2 (REL) is set to one. bit 1 (I/O) is cleared to zero. bit 0 (C/D) is cleared to zero. Sector Number, Cylinder High/Low, H n/a.

  • Page 128: Read Long (22H/23H)

    12.13 Read Long (22h/23h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 129 The head number of the sector to be transferred. ( L = 0 ) In LBA mode, this register contains LBA bits 24-27. ( L = 1 ) The retry bit. If set to one, then retries are disabled. Input Parameters From The Device Sector Count The number of requested sectors not transferred.

  • Page 130: Read Multiple (C4H)

    12.14 Read Multiple (C4h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 131 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 132: Read Native Max Lba/Cyl (F8H)

    12.15 Read Native Max LBA/CYL (F8h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 133: Read Sectors (20H/21H)

    12.16 Read Sectors (20h/21h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 134 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 135: Read Verify Sectors (40H/41H)

    12.17 Read Verify Sectors (40h/41h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 136 Input Parameters From The Device Sector Count The number of requested sectors not verified. This will be zero, unless an unrecover- able error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 137: Recalibrate (1Xh)

    12.18 Recalibrate (1xh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 138: Security Disable Password (F6H)

    12.19 Security Disable Password (F6h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 139: Security Erase Prepare (F3H)

    12.20 Security Erase Prepare (F3h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 140: Security Erase Unit (F4H)

    12.21 Security Erase Unit (F4h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 141 Identifier Zero indicates that the device should check the supplied password against the user password stored internally. One indicates that the device should check the given pass- word against the master password stored internally. The Security Erase Unit command erases all user data and disables the security mode feature (device lock function).

  • Page 142: Security Freeze Lock (F5H)

    12.22 Security Freeze Lock (F5h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 143: Security Set Password (F1H)

    12.23 Security Set Password (F1h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 144 W o r d D e s c r i p t i o n C o n t r o l w o r d b i t 0 : I d e n t i f i e r ( 1 M a s t e r , 0 U s e r ) b i t 1 7...

  • Page 145: Security Unlock (F2H)

    12.24 Security Unlock (F2h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 146 W o r d D e s c r i p t i o n C o n t r o l w o r d b i t 0 : I d e n t i f i e r ( 1 M a s t e r , 0 U s e r ) b i t 1 1 5...

  • Page 147: Seek (7Xh)

    12.25 Seek (7xh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 148: Service (A2H)

    12.26 Service (A2h) C o m m a n d B l o c k O u t p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 D a t a F e a t u r e S e c t o r C o u n t...

  • Page 149: Set Features (Efh)

    12.27 Set Features (EFh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 150 DDH Disable release interrupt Note 1. When Feature register is 03h ( = S e t Transfer mode), the Sector Count Register specifies the transfer mech- anism. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. PIO Default Transfer Mode 00000 000 PIO Default Transfer Mode,Disable IORDY...

  • Page 151: Set Max Lba/Cyl (F9H)

    12.28 Set Max LBA/CYL (F9h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 152 Cylinder High/Low In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High) which is to be set. ( L = 1 ) In CHS mode, this register contains cylinder number which is to be set.(L=0) In LBA mode, this register contains LBA bits 24 - 27 which is to be set.(L=1) In CHS mode, this register is ignored.

  • Page 153: Set Multiple (C6H)

    12.29 Set Multiple (C6h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 154: Sleep (E6H/99H)

    12.30 Sleep (E6h/99h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 155: Function Set (B0H)

    12.31 S.M.A.R.T. Function Set (B0h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 156 12.31.1.1 SMART Read Attribute Values (Subcommand D0h) This subcommand returns the device's Attribute Values to the host. Upon receipt of the SMART Read Attribute Values subcommand from the host, the device saves any updated Attribute Values to the Attribute Data sectors, and then transfers the 512 bytes of Attribute Value information to the host. 12.31.1.2 SMART Read Attribute Thresholds (Subcommand D1h) This subcommand returns the device's Attribute Thresholds to the host.
  • Page 157 Upon receipt of the subcommand from the host, the device sets BSY to one, begins or resumes its set of off-line activities, clears BSY to zero and asserts INTRQ. During execution of its off-line activities the device will not set BSY nor clear DRDY. 12.31.1.6 SMART Enable Operations (Subcommand D8h) This subcommand enables access to all S.M.A.R.T.

  • Page 158: Device Attributes Data Structure

    12.31.2 Device Attributes Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the SMART Read Attribute Values subcommand. All multi-byte fields shown in these data structures follow the ATA/ATAPI-4 specifications for byte ordering, namely that the least significant byte occupies the lowest numbered byte address location in the field.

  • Page 159: Individual Attribute Data Structure

    12.31.2.2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attri- bute Data Structure. D e s c r i p t i o n B y t e s O f f s e t F o r m a t A t t r i b u t e I D N u m b e r ( 0 1 h t o F F h ) 0 0 h...
  • Page 160 Seek Time Performance (*) Power-On Hours Count Spin Retry Count Device Power Cycle Count Ultra D M A C R C Error Count 12.31.2.2.2 Status Flag Definitions B i t F l a g N a m e D e f i n i t i o n P r e F a i l u r e / I f b i t = 0 , a n A t t r i b u t e V a l u e l e s s t h a n o r A d v i s o r y b i t...
  • Page 161 Bits 0 thru 6 represents a hexadecimal status value reported by the device. Value Definition Off-line data collection never started Segment completed without error All segments completed without errors. In this case, current segment pointer equals to total seg- ments required. Off-line data collecting aborted by interrupting command Off-line data collection aborted with fatal error 12.31.2.4 Total Segments Required for Off-line Data Collection...

  • Page 162: Device Attribute Thresholds Data Structure

    12.31.2.9 Data Structure Checksum The Data Structure Checksum is the 2's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data structure. 12.31.3 Device Attribute Thresholds Data Structure The following defines the 512 bytes that make up the Attribute Threshold information. This data structure is accessed by the host in its entirety using the SMART Read Attribute Thresholds.

  • Page 163: Error Reporting

    D e s c r i p t i o n B y t e s O f f s e t F o r m a t A t t r i b u t e I D N u m b e r ( 0 1 h t o F F h ) 0 0 h b i n a r y A t t r i b u t e T h r e s h o l d ( f o r c o m p a r i s o n w i t h...
  • Page 164 E r r o r C o n d i t i o n S t a t u s E r r o r R e g i s t e r R e g i s t e r A S .

  • Page 165: Standby (E2H/96H)

    12.32 Standby (E2h/96h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 166 Value Timeout ----------- --------------------------- Timer disabled 1 - 240 Value * 5 seconds 241 - 251 (Value-240) * 30 minutes 21 minutes 8 hours 21 minutes 10 seconds 21 minutes 15 seconds When the automatic power down sequence is enabled, the drive will enter Standby mode automatically if the timeout interval expires with no drive access from the host.

  • Page 167: Standby Immediate (E0H/94H)

    12.33 Standby Immediate (E0h/94h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 168: Write Buffer (E8H)

    12.34 Write Buffer (E8h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 169: Write Dma (Cah/Cbh)

    12.35 Write DMA (CAh/CBh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 170 The head number of the first sector to be transferred. ( L = 0 ) In LBA mode, this register contains LBA bits 24 - 27. ( L = 1 ) The retry bit. If set to one, then retries are disabled. But ignored, when write cache is enabled.

  • Page 171: Write Dma Queued (Cch)

    12.36 Write DMA Queued (CCh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 172 Input Parameters From The Device On Bus Release Sector Count bits 7 - 3 (Tag) contain the Tag of the command being bus released. bit 2 (REL) is set to one. bit 1 (I/O) is cleared to zero. bit 0 (C/D) is cleared to zero. Sector Number, Cylinder High/Low, H n/a.

  • Page 173: Write Long (32H/33H)

    12.37 Write Long (32h/33h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 174 Input Parameters From The Device Sector Count The number of requested sectors not transferred. Sector Number The sector number of the sector to be transferred. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the sector to be transferred.

  • Page 175: Write Multiple (C5H)

    12.38 Write Multiple (C5h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 176 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 177: Write Sectors (30H/31H)

    12.39 Write Sectors (30h/31h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 178 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 179: Timeout Values

    D a t a T r a n s f e r O u t B S Y = 1 B S Y = 0 a n d R D Y = 1 I n t e r r u p t Figure 128. Timeout Values Copyright IBM Corp. 1998...
  • Page 180 F U N C T I O N I N T E R V A L S T A R T S T O P T I M E O U T N o n D a t a D e v i c e B u s y A f t e r O U T t o C o m m a n d S t a t u s R e g i s t e r 4 0 0 n s...

  • Page 181: Appendix

    B 0 h S M A R T F U N C T I O N S E T Y e s O p t i o n a l ( 4 ) Figure 130. Command coverage Copyright IBM Corp. 1998...
  • Page 182 C o m m a n d C o m m a n d I m p l e m e n t a t i o n A T A 4 C o m m a n d C o d e N a m e f o r D T T A 3 X X X X X T y p e...

  • Page 183: Set Features Command Support Coverage

    14.2 SET FEATURES Command Support Coverage Following table is provided to facilitate the understanding of DTTA-3xxxxx "Set Features" command support coverage comparing to the ATA/ATAPI-4 defined command set. The column of 'Implementation' shows the capability of DTTA-3xxxxx for those commands. For detail operation, refer to 12.27, “Set Fea- tures (EFh)”...
  • Page 184 O E M Specifications for DTTA-3xxxxx...

  • Page 185: Index

    Security Erase Unit (F4h) Security Freeze Lock (F5h) Security Set Password (F1h) Hard Reset Security Unlock (F2h) Seek (7xh) Service (A2h) Set Features (EFh) Set Max LBA/CYL (F9h) Set Multiple (C6h) Sleep (E6h/99h) Standby (E2h/96h) Standby Immediate (E0h/94h) Copyright IBM Corp. 1998...
  • Page 186 Register (continued) Drive Address Register ICRCE Error Register Identify Device 89, 104 Features Register Idle 91, 110 Register Initialization Idle Immediate 92, 112 Sector Count Register I D N Sector Number Register I D N F Status Register Register Initialization Reset Initialize Device Parameters 92, 113...
  • Page 187 Timeout Interval Timeout Parameter 110, 157 Timeout Values TK0NF Write Buffer 90, 160 Write Cache Write D M A 92, 161 Write D M A Queued 93, 163 Write Long 90, 165 Write Multiple 90, 167 Write Sectors 90, 169 W T G Index...
  • Page 188 S00K-0286-02 Published in Japan...

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