Transcend TS64GSSD10-M Specification
Transcend TS64GSSD10-M Specification

Transcend TS64GSSD10-M Specification

1.0” solid state disk

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Description
The 1-inch Solid State Disk is small in size, has a
huge capacity and low power consumption making
it perfect for use as a mobile storage solution in
devices such as, Mobile Phones, PDA and GPS
systems. This guide is written to provide general
installation and handling information, please use it
in conjunction with the Owner's Manual for your
device or system.
Placement
Transcend Information Inc.
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Features
RoHS compliant
Fully compatible with 1.0-inch hard drive form factor
and interface (35-Pin FPC ZIF connector)
Non-volatile Flash Memory for outstanding data
retention
Built-in ECC (Error Correction Code) functionality and
wear-leveling algorithm ensures highly reliable of data
transfer
Mode Supports:
Ultra DMA Mode 0 to Mode 5
Multi-Word DMA Mode 0 to Mode 2
PIO Mode 0 to Mode 4
Supports ATA Security Commands
Support S.M.A.R.T function (self-definition)
Lower Power Consumption
Shock resistance
Power Supply: 3.3V ± 5%
Dimensions
Side
Millimeters
A
B
C
6
1.0" Solid State Disk
40.00 ± 0.30
1.575 ± 0.012
30.00 ± 0.20
1.181 ± 0.008
5.00 ± 0.50
0.196 ± 0.020
Inches
V1.6

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Summary of Contents for Transcend TS64GSSD10-M

  • Page 1 • Lower Power Consumption • Shock resistance • Power Supply: 3.3V ± 5% • Dimensions Side Millimeters Inches 40.00 ± 0.30 1.575 ± 0.012 30.00 ± 0.20 1.181 ± 0.008 5.00 ± 0.50 0.196 ± 0.020 Transcend Information Inc. V1.6...
  • Page 2: Environmental Specifications

    * Note: Reference to the IEC 60068-2-1 and IEC 60068-2-56 Testing procedures; 48-hours chamber test on ASUS ® M2N-MX, 1GB RAM, Windows XP Version 2002 SP2. Power Consumption Input Voltage DC 3.3V ± 5% Mode Maximum (mA) Power Consumption Write (DC 3.3V ℃ Read Standby Transcend Information Inc. V1.6...
  • Page 3 * Note : 25 ℃, test on ASUS M3N7B, 3GB RAM, IDE interface support UDMA5, Windows XP SP3, benchmark utility FDBENCH (version 1.02), copied file 100MB Actual Capacity Model P/N User LBA Cylinder Head Sector TS64GSSD10-M 125,059,072 16383 * Note: FAT32 format Regulations CE, FCC and BSMI Compliance Transcend Information Inc. V1.6...
  • Page 4: Mechanical Dimensions

    1.0” Solid State Disk Mechanical Dimensions Below figure illustrates the Transcend 1” Solid State Disk. All dimensions are in mm. Top View Lateral View Transcend Information Inc. V1.6...
  • Page 5: Solid State Disk

    1.0” Solid State Disk Pin Assignments Pin No. Pin Name Pin No. Pin Name DD10 -PDIAG -DASP -DMACK DMARQ DSTROBE -RESET -CSEL INTRQ -HIOW -HIOR -CS1 -CS0 DD15 DD14 DD13 DD12 DD11 Pin Layout Transcend Information Inc. V1.6...
  • Page 6: Block Diagram

    High level output voltage – 0.8 Low level output voltage Non-schmitt trigger High level input voltage 2.05 Schmitt trigger Non-schmitt trigger Low level input voltage 1.25 Schmitt trigger Pull up resistance 52.7 KOhm Pull down resistance 47.5 kOhm Transcend Information Inc. V1.6...
  • Page 7 Ultra DMA mode. Shows signals also requiring a pull-up or pull-down resistor at the host. The actual termination values should be selected to compensate for transceiver and trace impedance to match the characteristic cable impedance. Electrical Characteristics Parameter Value Frequency Stability 30-80MHz Transcend Information Inc. V1.6...
  • Page 8 HIOR# or HIOW# activation, then t5 is met and tRD is not applicable. When the PATA is driving DSTROBE, which is negated at the time tA after HIOR# or HIOW#, then tRD is met and t5 is not applicable. 4) DSTROBE is not supported in this mode. Transcend Information Inc. V1.6...
  • Page 9 : a wait is generated. The cycle is completed after DSTROBE is reasserted. For cycles in which a wait is generated and HIOR# is asserted, the device places read data on D15-D00 for t before DSTROBE is asserted. Transcend Information Inc. V1.6...
  • Page 10 DMACK# to HIOR#/HIOW# setup (min) HIOR# / HIOW# to DMACK# hold (min) HIOR# negated width (min) HIOW# negated width (min) HIOR# to DMARQ delay (max) HIOW# to DMARQ delay (max) CSx valid to HIOR# / HIOW# CSx hold Transcend Information Inc. V1.6...
  • Page 11 NOTE-The host shall not assert DMACK- or negate both CS0 and CS1 until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK- or the negation of both CS0 and CS1 is not defined. Sustaining a Multiword DMA data burst Transcend Information Inc. V1.6...
  • Page 12 HIOR- or HIOW- pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation as shown in figure True IDE PIO Mode Read/Write Timing. Transcend Information Inc. V1.6...
  • Page 13 2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK- or may negate DMARQ at any time after detecting that DMACK has been negated. Transcend Information Inc. V1.6...
  • Page 14 3) The parameter tCYC shall be measured at the recipient’s connector farthest from the sender. 4) The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing Transcend Information Inc. V1.6...
  • Page 15 DSTROBEZ Minimum time before driving DSTROBE 4, 6 ZDSTROBE Setup and hold times for -DMACK (before assertion or negation) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) Transcend Information Inc. V1.6...
  • Page 16 3) The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources has not been included in these values. Transcend Information Inc. V1.6...
  • Page 17: Initiating An Ultra Dma Data-In Burst

    1.0” Solid State Disk Initiating an Ultra DMA data-in burst Note: The definitions for the HIOW-:STOP, HIOR-:HDMARDY-:HSTROBE, and DSTROBE:DDMARDY-:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Transcend Information Inc. V1.6...
  • Page 18: Host Pausing An Ultra Dma Data-In Burst

    1.The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated. 2.After negating HDMARDY-, the host may receive zero, one, two, or three more data words from the device. Transcend Information Inc. V1.6...
  • Page 19: Device Terminating An Ultra Dma Data-In Burst

    1.0” Solid State Disk Device terminating an Ultra DMA data-in burst Note: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Transcend Information Inc. V1.6...
  • Page 20: Host Terminating An Ultra Dma Data-In Burst

    1.0” Solid State Disk Host terminating an Ultra DMA data-in burst Note: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Transcend Information Inc. V1.6...
  • Page 21: Initiating An Ultra Dma Data-Out Burst

    Note: DD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host. Transcend Information Inc. V1.6...
  • Page 22: Device Pausing An Ultra Dma Data-Out Burst

    1.The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY- is negated. 2 After negating DDMARDY-, the device may receive zero, one, two, or three more data words from the host. Transcend Information Inc. V1.6...
  • Page 23 1.0” Solid State Disk Host terminating an Ultra DMA data-out burst Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Transcend Information Inc. V1.6...
  • Page 24 1.0” Solid State Disk Device terminating an Ultra DMA data-out burst Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Transcend Information Inc. V1.6...
  • Page 25: Command Set

    Security Freeze Lock – – – – – Support Security Set Password – – – – – Support Security Unlock – – – – – Support Seek – – Not Support Set Feature – – – – Support Transcend Information Inc. V1.6...
  • Page 26 SN = Sector Number register CY = Cylinder Low/High register DH = Head No. (0 to 15) of Drive/Head register LBA = Logic Block Address Mode Support – = Not used for the command Y = Used for the command Transcend Information Inc. V1.6...
  • Page 27: Smart Command Set

    X=the content of the byte is vendor specific and may be fixed or variable. R=the content of the byte is reserved and shall be zero. * 4 Byte value : [MSB] [2] [1] [LSB] Transcend Information Inc. V1.6...
  • Page 28 SMART self-test log Device vendor specific Note: RO - Log is read only by the host. R/W - Log is read or written by the host. VS - Log is vendor specific thus read/write abiltiy is vendor specific. Transcend Information Inc. V1.6...
  • Page 29: Identify Device (Ech)

    Maximum number of sectors on Read/Write Multiple command 0000h Reserved 0F00h Capabilities 0000h Reserved 0200h PIO data transfer cycle timing mode 0000h Obsolete 0007h Field Validity 3FFFh (16383) Current numbers of cylinders 000Fh (15) Current numbers of heads Transcend Information Inc. V1.6...
  • Page 30 CFA Power mode 0000h Reserved for assignment by the CFA 0000h Key management schemes supported 0000h CF Advanced True IDE Timing Mode Capability and Setting 0000h CF Advanced PC Card I/O and Memory Timing Mode Capability Transcend Information Inc. V1.6...
  • Page 31 1.0” Solid State Disk 165-175 0000h Reserved 176-255 0000h Reserved Transcend Information Inc. V1.6...

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