Package C-States; Coordination Of Core Power States At The Package Level - Intel BX80623I32100 Datasheet

4.2.5

Package C-States

The processor supports C0, C1/C1E, C3, and C6 power states. The following is a
summary of the general rules for package C-state entry. These apply to all package C-
states unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor.
— For package C-states, the processor is not required to enter C0 before entering
any other C-state.
The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:
• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0.
• If the break event was due to a memory access or snoop request.
— But the platform did not request to keep the processor in a higher package C-
state, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or snoop
request is serviced and the package remains in the higher power C-state.
Table 4-10. Coordination of Core Power States at the Package Level
Package C-State
Core 0
Note:
1. If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.
50
C0
C0 C0
C1 C0
C3 C0
C6 C0
Core 1
C1 C3
C0 C0
1 1
C1 C1
1
C1 C3
1
C1 C3
Power Management
C6
C0
1
C1
C3
C6
Datasheet, Volume 1