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Note: Since no bit clock is available, the recommended approach for
calculating CRC is to use a word clock derived from the bus strobe. The
combinational logic shall then be equivalent to shifting sixteen bits serially
through the generator polynominal where DD0 is shifted in first and DD15 is
shifted in last.
DD0–DD15
16
Figure 5.8 An example of generation of parallel CRC
Table 5.14 Parallel generation equation of CRC polynomial
CRCINO=f
16
CRCIN1=f
15
CRCIN2=f
14
CRCIN3=f
13
CRCIN4=f
12
CRCIN5=f
XOR f
11
CRCIN6=f
XOR f
10
CRCIN7=f
XOR f
9
f
= DD0 XOR CRCOUT
1
f
= DD1 XOR CRCOUT
2
f
= DD2 XOR CRCOUT
3
f
= DD3 XOR CRCOUT
4
f
= DD4 XOR CRCOUT
5
f
= DD5 XOR CRCOUT
6
f
= DD6 XOR CRCOUT
7
f
= DD7 XOR CRCOUT
8
DD :
Data from bust
CRCIN : Output of combination logic (the next CRC)
CROUT : Result of 16 bit latch (current CRC)
C141-E057-01EN
CRCIN
F1–f16
16
Combination
logic
16
CRCIN8 = f
CRCIN9 = f
CRCIN10 = f
CRCIN11 = f
CRCIN12 = f
CRCIN13 = f
CRCIN14 = f
15
CRCIN15 = f
14
f
= DD8 XOR CRCOUT7 XOR f
15
9
f
= DD9 XOR CRCOUT6 XOR f
14
10
f
= DD10 XOR CRCOUT5 XOR f
13
11
f
= DD11 XOR CRCOUT4 XOR f
12
12
XOR f
f
= DD12 XOR CRCOUT3 XOR f
11
1
13
XOR f
f
= DD13 XOR CRCOUT2 XOR f
10
2
14
XOR f
f
= DD14 XOR CRCOUT1 XOR f
9
3
15
XOR f
f
= DD15 XOR CRCOUT0 XOR f
8
4
16
f : Feedback
5.5 Ultra DMA Feature Set
CRCOUT
Latch
Word
clock
XOR f
8
13
XOR f
7
12
XOR f
6
11
XOR f
5
10
XOR f
XOR f
4
9
16
XOR f
XOR f
3
8
15
XOR f
XOR f
2
7
14
XOR f
XOR f
1
6
13
16
5
6
7
XOR f
1
8
XOR f
2
9
XOR f
3
10
XOR f
4
11
XOR f
5
12
5-93
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