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Interface
1F7
1F6
1F5
1F4
1F3
1F2
1F1
1F7
1F6
1F5
1F4
1F3
1F2
1F1
(7) WRITE DMA (X'CA' or X'CB')
This command operates similarly to the WRITE SECTOR(S) command except for
following events.
The data transfer starts at the timing of DMARQ signal assertion.
The device controls the assertion or negation timing of the DMARQ signal.
The device posts a status as the result of command execution only once at
completion of the data transfer or completion of processing in the device.
The device posts a status as the result of command execution only once at
completion of the data transfer.
When an error, such as an unrecoverable medium error, that the command
execution cannot be continued is detected, the data transfer is stopped without
transferring data of sectors after the erred sector. The device generates an
interrupt using the INTRQ signal and posts a status to the host system. The
format of the error information is the same as the WRITE SECTOR(S) command.
5-26
At command issuance (I/O registers setting contents)
(CM)
1
1
H
(DH)
L
H
(CH)
Start cylinder No. [MSB] / LBA
H
(CL)
Start cylinder No. [LSB] / LBA
H
(SN)
Start sector No. / LBA [LSB]
H
(SC)
Transfer sector count
H
(FR)
xx
H
At command completion (I/O registers contents to be read)
(ST)
Status information
H
(DH)
L
H
(CH)
End cylinder No. [MSB] / LBA
H
(CL)
End cylinder No. [LSB] / LBA
H
(SN)
End sector No. / LBA [LSB]
H
(SC)
00
H
(ER)
Error information
H
0
0
0
1
DV
Start head No. /LBA [MSB]
DV
End head No. /LBA [MSB]
0
1
C141-E057-01EN
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