AMD Am79C930 Preliminary Manual page 88

AMD
TIR mapping with SIR1 bit 2 (EIOW) set to "1" = Ex-
panded TIR window mode. Note that the setting
TIR
Register
Number TIR Register Name
0 Network Control
1 Network Status
2 Serial Device
3 Fast Serial Port Control
4 Interrupt Register 1
5 Interrupt Register 2
6 Interrupt Mask 1
7 Interrupt Mask 2
8 Transmit Control
9 Transmit Status
10 TX FIFO Data
11 Transmit Sequence Control
12 Byte Counter LSB
13 Byte Counter MSB
14 Byte Counter Limit LSB
15 Byte Counter Limit MSB
16 Receiver Control
17 Receiver Status
18 RX FIFO Data
19 Antenna Slot
20 CRC32 Correct Count LSB
21 CRC32 Correct Count MSB
22 CRC8 Correct Count LSB
23 CRC8 Correct Count MSB
24 Configuration Index
25 Configuration Data Port
26 Antenna Diversity & A/D
27 SAR
28 RSSI Lower Limit
29 USER Pin Data
30 Dummy Register
31 TEST Register
*XX = Don't care.
88
P R E L I M I N A R Y
EIOW = 1 is only allowed while operating in PCMCIA
mode. TIR uses 32 I/O addresses:
SIR1[1:0]
(TAI Bank
Select)
XX*
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
Am79C930
80188 Core
PCMCIA Address in
I/O Address Memory
0008h mem 400h
0009h mem 401h
000Ah mem 402h
000Bh mem 403h
000Ch mem 404h
000Dh mem 405h
000Eh mem 406h
000Fh mem 407h
0010h mem 408h
0011h mem 409h
0012h mem 40Ah
0013h mem 40Bh
0014h mem 40Ch
0015h mem 40Dh
0016h mem 40Eh
0017h mem 40Fh
0018h mem 410h
0019h mem 411h
001Ah mem 412h
001Bh mem 413h
001Ch mem 414h
001Dh mem 415h
001Eh mem 416h
001Fh mem 417h
0020h mem 418h
0021h mem 419h
0022h mem 41Ah
0023h mem 41Bh
0024h mem 41Ch
0025h mem 41Dh
0026h mem 41Eh
0027h mem 41Fh