Page 1: Distinctive Characteristics
LAN connection. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Page 2: Ordering Information
ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. AM79C930 DEVICE NUMBER/DESCRIPTION Am79C930 Single-Chip Wireless LAN Media Access Controller Valid Combinations...
Page 3: Block Diagram
TEST PWRDWN P R E L I M I N A R Y CA16–8 CAD 7–0 DRQ0 INT1 DRQ1 INT0 Control Unit (80188 core) SRDY RESET Am79C930 TRST JTAG TMS/T3 Control TDI/T1 Block TDO/T2 RXCIN ANTSLT ANTSLT SAR6–0 ADIN2–1 ADREF...
Page 4: Bus Interface Unit
Slave Control PCMCIA and ISA Memory and I/O PCMCIA Config Registers Plug and Play Control Module 80188 ISA Memory Base Interrupt Generator ISA I/O Base Am79C930 CA16 Latch CA15–8 CAD7–0 MIR0 MIR1 MIR15 Slave Control Arbitration SRDY Memory Interface TAICE...
Page 5: Transceiver Attachment Interface Unit
P R E L I M I N A R Y Transceiver Interface Unit Control TCR0 TCR... FIFO TCR31 Bytes P->S ÷80 BIAS Suppress ÷40 ÷5 Sleep ÷10 ÷20 Am79C930 Transceiver Control Signals FIFO Bytes S->P FDET Detect Count Phylen 20183B-3...
Page 6: Table Of Contents
............Am79C930...
Page 7 ................. . . Am79C930...
Page 8 ..............TX Power Ramp Control Am79C930-based TX Power Ramp Control . Transceiver-Based TX Power Ramp Control .
Page 9 ........... Am79C930...
Page 10 ........... . Am79C930...
Page 11 ............. . 5.0 V Am79C930 DC Characteristics 3.3 V Am79C930 DC Characteristics...
Page 12: Pcmcia Block Diagram
............. APPENDIX A: Typical Am79C930 System Application Device Configuration .
Page 13: Pcmcia Connection Diagram
MA16 MA15 MA12 VDDM VSSM VDDM VSSM Notes: Pin 1 is marked for orientation. NC = No Connection P R E L I M I N A R Y Am79C930 Am79C930 SAR0 SDSEL1 VSST SDSEL2 VDDT SDSEL3 ADDATA SDCLK VSST...
Page 14: Pcmcia Pin Summary
USER1 USER7 VSSU1 RESET USER6 USER5 IREQ VDDU1 VSST SDCLK IOWR SDDATA IORD SDSEL3 VDDT SDSEL2 VSST SDSEL1 SAR0 Am79C930 Pin No. Pin Name SAR1 SAR2 SAR3 SAR4 SAR5 SAR6 VSST LFCLK LFPE HFCLK HFPE TXDATA RXPE RXDATA RXCIN VDDT...
Page 15: Pcmcia Pin List
SAR0 SAR1 SAR2 SAR3 SAR4 SAR5 SAR6 SDCLK SDDATA SDSEL1 SDSEL2 SDSEL3 STSCHG TEST TRST TXCMD TXCMD TXDATA TXDATA Am79C930 Pin Name Pin No. TXMOD TXPE USER0 USER1 USER2 USER3 USER4 USER5 USER6 VDD5 VDDM VDDM VDDM VDDP VDDT VDDT...
Page 16: Pcmcia Pin Function Summary
SRAM, and/or an extra peripheral device within an Am79C930-based design Flash Chip Enable—this signal becomes asserted when the Flash device has been addressed by either the 80188 core of the Am79C930 device or by the software through the PCMCIA interface SRAM Chip Enable—this signal becomes asserted when the SRAM device...
Page 17 Test Reset—this is the reset signal for IEEE 1149.1 testing USER7 User-programmable pin Receive Clock—provides decode receive clock Test pin—when asserted, this pin places the Am79C930 device into a TEST nonstandard factory-only test mode Clock input to drive BIU, 80188 core, and TAI, supplying network data rate...
Page 18 Pin Function Type 4 mA 4 mA 24 mA 4 mA 12 mA 24 mA 24 mA Type Size of Pullup Am79C930 Pin Style PTS3, PTS1 Load –4 mA 50 pF –4 mA 50 pF –4 mA 120 pF –4 mA 50 pF –4 mA...
Page 19: Isa Plug And Play Block Diagram
P R E L I M I N A R Y CA16–18 CAD 7–0 DRQ0 IEEE INT1 DRQ1 802.11 INT0 Control Unit (80188 core) RESET SRDY RESET Am79C930 TRST JTAG TMS/T3 Control TDI/T1 Block TDO/T2 RXCIN ANTSLT ANTSLT SAR6–0 ADIN2–1 ADREF...
Page 20: Connection Diagram
MA16 MA15 MA12 VDDM VSSM VDDM VSSM Notes: Pin 1 is marked for orientation. NC = No Connection P R E L I M I N A R Y Am79C930 Am79C930 SAR0 SDSEL1 VSST SDSEL2 VDDT SDSEL3 ADDATA SDCLK VSST...
Page 21: Isa Plug And Play Pin List
IRQ4 IRQ9 VDDU1 MEMW SA14 VSST SA13 SDCLK SDDATA SDSEL3 VDDT SA11 SDSEL2 MEMR VSST SA10 SDSEL1 LA18 SAR0 Am79C930 Pin No. Pin Name SAR1 SAR2 SAR3 SAR4 SAR5 SAR6 VSST LFCLK LFPE HFCLK HFPE TXDATA RXPE RXDATA RXCIN VDDT...
Page 22: Listed By Pin Name
SA10 SA11 SA12 SA12 SA13 SA14 SA15 SA16 SAR0 SAR1 SAR2 SAR3 SAR4 SAR5 SAR6 SDCLK SDDATA SDSEL1 Am79C930 Pin No. Pin Name Pin No. SDSEL2 SDSEL3 TEST TRST TXCMD TXDATA TXMOD TXPE VDD5 VDDM VDDM VDDM VDDP VDDT VDDT...
Page 23: Isa Plug And Play Pin Summary
SRAM, and/or an extra peripheral device within an Am79C930-based design Flash Chip Enable—this signal becomes asserted when the Flash device has been addressed by either the 80188 core of the Am79C930 device or by the software through the PCMCIA interface SRAM Chip Enable—this signal becomes asserted when the SRAM device...
Page 24 P R E L I M I N A R Y Pin Function Type 4 mA 4 mA 24 mA 4 mA 12 mA 24 mA 24 mA Output Type Size of Pullup Am79C930 Pin Style PTS1 PTS1 PTS1 PTS1 PTS1 PTS1 PTS1 PTS2 PTS2 load –4 mA 50 pF –4 mA...
Page 25: Pin Descriptions
(pull-device or driver) connected and the INITDN bit of MIR9 set to a 1, since this could lead to unaccept- able levels of power consumption by the Am79C930 de- vice. For more information on programmable pins, see the Multi-Function Pins section.
Page 26: Pcmcia Bus Interface
Output Enable USER5/IRQ4 OE is an active low-output-enable input signal. OE is LA17 used to gate memory read data from the Am79C930 de- SA16 vice onto the PCMCIA data bus. OE should be deas- LA19 serted during memory write cycles to the Am79C930 device.
Page 27: Isa (Ieee P996) Bus Interface
Card Configuration Option Register CCOR) and places the Am79C930 device into an unconfigured (PCMCIA- Memory-Only Interface) state. This pin also causes a RESET to be asserted to each of the Am79C930 core function units (i.e., PCMCIA interface, CPU, and Trans- ceiver Attachment Interface).
Page 28 ISA bus outputs into a high imped- ance state. This pin also causes a RESET to be as- serted to each of the Am79C930 core function units (i.e., ISA interface state machine, 80188, and Transceiver Attachment Interface).
Page 29: Clock Pins
Some systems may require that the Am79C930 device deliver the transmit data according to a clock reference that is external to the Am79C930 device. In such sys- tems, the TXC pin may be configured as an input. TXDATA will change on falling edges of TXC, allowing ample setup and hold time for valid sampling of TXDATA with the rising edge of TXC.
Page 30 Data and FCS field. The RXDATA input stream is expected to be NRZ data. Clock recovery is per- formed internal to the Am79C930 device. If an external P R E L I M I N A R Y PLL is used for clock recovery, then the RXDATA input will expect valid data at rising edges of the RXCIN input.
Page 31: Other Pins
ADIN[1–2] A/D sample inputs ADIN[1–2] are inputs that accept single-ended analog input values for conversion by the internal Am79C930 P R E L I M I N A R Y A/D converter. Only one input will be sampled at any time for conversion by the internal Am79C930 device’s...
Page 32: Ieee 1149.1 Test Access Port Pins
TTL or CMOS level at all times. TCK must not be left unconnected. Test Data Input TDI is the test data input path to the Am79C930 device. If left unconnected, this pin has a default value of HIGH. Test Data Output TDO is the test data output path from the Am79C930 de- vice.
Page 33: Multi-Function Pins
3 V systems, these pins should be connected to a Ground ground supply. Multi-Function Pins The Am79C930 device includes a number of pins which have multiply-defined functions. The various functions assigned to each of these pins is determined through both device pin settings and through individual register Power bit settings.
Page 34: Pin 1: User2/La19
The USER0/RFRSH pin may be configured for input op- eration, output operation, or ISA RFRSH operation ac- cording to the following table: PCMCIA USER4/ LA17 Pin Data (LA17 input function) TIR29[4] Am79C930 STSCHG/ STSCHG/ BALE BALE TCR15[0] Pin Direction Pin Data (BALE input...
Page 35: Pin 91: User1/Irq12/Extcts/Exint188
PnPx70 PnPx71 to control the start of the TX state machine, provided that Am79C930 device firmware has enabled the operation by setting the TXS bit of TIR8. In addition to the functionality listed above, the USER1/IRQ12/EXTCTS/EXINT188 pin may be used to produce interrupts to the 80188 embedded controller.
Page 36: Pin 94: Rxc/Irq10/Exta2Dst
In addition to the functionality listed above, the USER6/IRQ5/EXTSDF pin may be used to enable the function of the RX state machine within the Am79C930 device. This capability is controlled by the ENXSDF bit and the ENXCHBSY bit, both of TCR28. When the...
Page 37: Pin 98: Act
USER5/IRQ4/EXTCHBSY pin may be used as the source for CCA information, instead of relying on the in- ternal CCA logic of the Am79C930 device. When using the external CCA information, CCA information from the internal logic will be unavailable. External CCA informa-...
Page 38: Pin 101: Sdclk
SDSEL[1] pin value without inversion, regardless of pin configuration setting. SDSEL[1] SDSEL[1] Pin Direction Pin Value HIGH Am79C930 reset default condition (when write to TIR2 occurs) (when write to TIR2 occurs) reset default condition reset default condition reset default condition...
Page 39: Pin 115: Txc
CLKIN input. Since the external TXC source is not driving the Am79C930 device TX state machine, there exists a TXCIN TCR30[3] Pin 118: LFPE...
Page 40: Pin 126: Txcmd
TXCMD bit of TIR11 (TIR11[0]), according to the following table: TXCMD Pin Direction diagram in section Am79C930-Based TX Power Ramp Control. Transmit state machine generated signals T1, T2, T3, TXP _ ON and O_TX have the timing indicated in the diagram in section Am79C930-Based TX Power Ramp Control.
Page 41: Pin 142: Txcmd/La21
Direction Transmit state machine generated signals T1, T2, T3, TXP _ ON and O_TX have the timing indicated in the diagram in section Am79C930-Based TX Power Ramp Control. Note that a read of the TXCMDT bit (TCR7[2]) will al- ways give the current TXCMD/LA21 pin value without inversion, regardless of pin configuration setting.
Page 42: Functional Description
Memory Bus Interface Function The Am79C930 device contains a memory bus inter- face, which is used by the Am79C930 device to gain ac- cess to Flash memory for fetching 80188 instructions and to gain access to SRAM for fetching and storing driver commands, network data, and for temporary vari- able storage.
Page 43: Pcmcia Interface
Am79C930-based design resides. The Common memory slave response function is always ac- tive on the Am79C930 device; it is not possible to dis- able this function. The Am79C930 device does not attempt to interpret the ConfIndex value of the PCMCIA Configuration Option Register except for purposes of enabling the I/O slave response function.
Page 44: Isa (Ieee P996) Plug And Play Interface
Am79C930 device fully supports the ISA Plug and Play specification, revision 1.0a. The ISA Plug and Play interface on the Am79C930 de- vice supports both memory and I/O cycles. The data bus is 8 bits in width. The total system space required by the Am79C930 device is 32 Kbytes and 16 bytes of I/O space.
Page 45: Memory Interface
TAI. A separate internal chip select signal for the TAI exists to avoid confusion among slave devices. This sig- nal is not available on the Am79C930 memory interface bus, and therefore, memory interface cycles may be ob- served for which neither the Flash chip enable, nor the SRAM chip enable, nor the XCE signal is asserted.
Page 46: Initialization
The SCE signal may be attached to the CE in- put of an SRAM memory device external to the Am79C930 device. Up to 128K of SRAM may be ad- dressed by the 80188 core (with the exception that 64 bytes of SRAM space is mapped into internal Am79C930 registers of the BIU and TAI.)
Page 47: Flash Memory Management
The 80188 core accesses the Flash memory by assert- ing its Upper Chip Select (80188 UCS) This signal remains internal to the Am79C930 device. The internal UCS signal is routed into the BIU, since the 80188 core and the BIU must share the memory interface bus. The...
Page 48: Tx Fifo
10, while the fixed function pins remain unchanged. The TAI is logically located on the Am79C930 memory interface bus as a slave-only device. The TAI contains 64 registers that are used to configure operational pa- rameters, to communicate commands, to pass data, and to pass status.
Page 49 The polarity of TXMOD and TXPE are programmable. A separate TXCMD signal (inverse polarity to TXCMD) is available. When RCEN=1 Am79C930 TGAP4 X TBCLK + 2 X TSCLK TGAP3 X TBCLK + 2 X TSCLK 2 X TSCLK...
Page 50: Transceiver-Based Tx Power Ramp Control
CTS signal is enabled by setting the CTSEN bit of TCR7 to a 1, then the CTS input acts as a gating signal with respect to the start of the Am79C930 transmit op- erations. An example of the use of the CTS signal would be when a transceiver is in control of the decision to transmit.
Page 51: Rx Status Reporting
The SAR pins are used as inputs in this mode to allow the externally converted value to be driven back into the Am79C930 device, so that it may be used in the CCA and Antenna Diversity logic circuits. In this mode, ADIN1 functions as the power control signal.
Page 52: Physical Header Accommodation
Because antenna switching can cause transient noise reserved to appear at the RXD input of the Am79C930 device, the D/A mode start of Baud Determination testing is delayed for a pe- riod of time immediately following the antenna switching process.
Page 53: Clear Channel Assessment Logic
Am79C930 device’s internal CCA logic, which is de- scribed in the following paragraphs. The other possible CCA source is externally computed CCA information, which is then passed into the Am79C930 device through the USER5/IRQ4/EXTCHBSY pin. Regardless of the source of CCA information, a path through the...
Page 54: Automatic Antenna Diversity Logic
RSSI input value exceeds the programmed lower limit, then the result of this test is considered to be TRUE. The two tests mentioned above may be separately selected/deselected to serve as inputs to the Stop Am79C930 CCA Result (CHBSY Bit of TIR26) CHBSY = TRUE...
Page 55: Txc As Input
However, for some transceiver connections, the signal TXC is de- fined as a transceiver output . The Am79C930 device can accommodate both types of transceivers by allow- ing the TXC pin to be defined as either output or input.
Page 56: Boundary Scan Circuit
Power Saving Modes Power Down Function The Am79C930 BIU includes five registers that are used to invoke a power-down function that will support the IEEE 802.11 (draft) specified power down by allowing variable lengths of power-down and power-up time. The...
Page 57 P R E L I M I N A R Y If the Am79C930 device is operating in the ISA Plug and Play mode, then SIR0, SIR1, SIR2, and SIR3 registers will be the only locations that are still accessible when the Am79C930 device is in the power down mode.
Page 58: Applicability To Ieee 802.11 Power Down Modes
Power Down Length Count register values for each power down cycle. Software Access The Am79C930 device is directly driven by two pieces of software: (1) the device driver, which runs on the host machine’s CPU, performs transfers of data between the...
Page 59 Local Memory Address Register and I/O Data Ports (SIR2,3,4,5,6,7), it is possible to assign the Am79C930 device no memory space. (This is accomplished by setting the MemSpace field of the TPCE_FS byte of the Configuration Table Entry Tuple to 00b.
Page 60 Some of the Am79C930 device’s PCMCIA Common Memory locations have predefined uses and, therefore, are not freely available to the device driver. Am79C930 Device PCMCIA Mode Common Memory Restricted Space PCMCIA Address in Common Memory SIR1[5:3] 0000h – 03FFh 0400h – 041Fh 0420h –...
Page 61: Pcmcia Attribute Memory Resources
PCMCIA CIS information, since these bytes map to the upper 16 bytes of the Flash memory, which will be used by the 80188 core of the Am79C930 as the initial instruc- tion locations after reset. Note that the Configuration Tuple must contain the...
Page 62: Pcmcia I/O Resources
16 or 40 bytes of I/O space, depending upon the setting of the EIOW bit (bit 2 of the BSS register (SIR1)). The I/O space of the Am79C930 contains the General Configuration Register, the Bank Switching Se- lect Register, and the set of 32 TIR registers. Addition- ally, all Am79C930 resources are accessible through I/O accesses, i.e., all memory structures are accessible...
Page 63: Isa Plug And Play Mode Resources
Flash memory for reading the Am79C930 device’s Plug and Play Resource Data. The following table indicates the range of I/O and mem- ory addresses to which the Am79C930 device will re- spond when operating in the ISA Plug and Play mode. Am79C930...
Page 64: Isa Plug And Play Memory Resources
Am79C930 Device ISA Plug And Play Mode Memory And I/O Resource Requirements Memory Range Memory Size MBA*+0000h – 32 Kbytes MBA*+7FFFh 0 bytes *MBA = ISA Plug and Play Memory Base Address **IOBA = ISA Plug and Play I/O Base Address Note that since the Am79C930 device’s memory...
Page 65 Am79C930 device’s Bus Interface Unit will only use the upper 9 bits of the ISA memory address to determine when an address match has been achieved. Am79C930 Device ISA Plug And Play Mode Memory Restricted Space ISA Address in Memory SIR1[5:3] MBA+0000h –...
Page 66: Isa Plug And Play I/O Resources
ISA Plug and Play mode of operation. The EIOW bit (bit 2 of the BSS register (SIR1)) will be forced to 0 when the Am79C930 device has been placed into ISA Plug and Play mode. The I/O...
Page 67 Am79C930 Device ISA Plug And Play Mode I/O MAP Resource Name Mnemonic SIR0: General SIR0: GCR Configuration Register SIR1: Bank Switching SIR1: BSS Select Register SIR2: Local Memory SIR2: LMAL Address [7:0] SIR3: Local Memory SIR3: LMAU Address [14:8] SIR4: I/O Data Port [7:0]...
Page 68: Isa Plug And Play Register Set
ISA Plug and Play Register Set — The Am79C930 de- vice fully supports the ISA Plug and Play specification, revision 1.0a. The Am79C930 device supports the Plug and Play Auto-configuration scheme. The Plug and Play Am79C930 Device ISA Plug And Play Mode Supported Auto-Configuration Ports...
Page 69 Am79C930 Device ISA Plug And Play Mode Plug And Play Register Set ISA Plug and Play Register Name Set READ_DATA port Serial Isolation Configuration Control Wake [CSN] Resource Data Status Card Select Number (CSN) Logical Device Number Unused Activate I/O Range Check...
Page 70: Mac Firmware Resources
1K–16 of the upper 1 Kbytes of the Flash memory space so that Resource Data may be read from the Flash memory. Byte 0 of the Am79C930 device’s Resource Data is mapped to location 1 FC00h of the Flash memory. A maximum of 1K–16 bytes of Re- source Data is allowed by the Am79C930 design.
Page 71 0 8000h–1 FFFFh don’t care 2 0000h–D FFFFh none E 0000h–F FFFFh P R E L I M I N A R Y Active Am79C930 Size of Chip Select Space 1 Kbytes SRAM Memory 0 0000h–0 03FFh none 32 bytes...
Page 72: Mac (80188 Core) Memory Resources Restrictions
F FC00h–F FFEFh F FFF0h–F FFFFh MAC (80188 core) Interrupt Channel Allocation — The TAI and BIU sections of the Am79C930 device both generate interrupts to the 80188 core. TAI generated in- terrupts will always appear on the INT0 input of the 80188 core.
Page 73: Dma Channel Allocation In The 80188 Core
The Am79C930 device contains a loopback mode that is invoked by writing a 1 to the LOOPB bit of TCR3[7]. When LOOPB is set to a 1, then the Am79C930 device will perform an internal loopback of all transmissions. The data path transmitted will move out of the TX FIFO and be serialized.
Page 74: Coreset (Sir0[6])
The CORESET bit of SIR0[6] can be used to reset the embedded controller and TAI sections of the Am79C930 device, along with a few locations in the MIR register space. When the CORESET bit is asserted, then the 80188 section of the Am79C930 device will be...
Page 75: Isa Pnp Reset
“111b” to bits two through zero of this register (i.e., bits [2:0]) will cause an internal RESET pulse to occur within the Am79C930 device). The RESET pulse will last for 14 CLKIN periods. This RESET will have the same effect as asserting the...
Page 76: System Interface Registers (Sir Space)
The TIR space contains 32 registers which are used by the 80188 core to control the Am79C930 device’s TAI unit, to collect TAI status, and to transfer data to and from the TAI. These registers are accessible from both the system interface and the 80188 core.
Page 77: Sir0: General Configuration Register (Gcr)
Disable Power Down Mode. When DISPWDN is set to a 1, the Am79C930 device will be prevented from entering the power down mode. If the Am79C930 device is already in the power down mode when DISPWDN notes a transition from 0 to 1, then the power down mode will be exited within three CLKIN periods.
Page 78: Sir1: Bank Switching Select Register (Bss)
I/O offsets 0008h through 0027h. EIOW is always 0 when the Am79C930 device has been set to the ISA Plug and Play mode of operation. EIOW is not writeable when the Am79C930 device has been set to the ISA Plug and Play mode of operation.
Page 79: Sir2: Local Memory Address Register [7:0] (Lma)
BSS[4:3] – memory bank select bits.) Description – These 8 bits act as Am79C930 memory interface bus address bits MA[7:0] during system interface accesses to Flash and SRAM whenever any section of the I/O Data port is read or written. The LMA[14:0] value is automatically incremented by R1S after any section of the I/O Data Port is read or written.
Page 80: Sir5: I/O Data Port B (Iodpb)
BIU is in direct memory access mode, such that system interface access cycles will have direct access to the Am79C930 memory interface. This mode should only be in- voked if the 80188 will be placed into HALT mode by an appropriate instruction within the 80188 firmware during the time that SIDA is set to 1.
Page 81: Mir1: Power Up Clock Time [3:0] (Puct)
Lower 8 bits of the length of the power down cycle counter. The resolution of the power down length counter is in increments of PMX1/2 periods. The nominal PMX1/2 crystal Value is 32.768 kHz, resulting in a resolution of 31.25 s. Am79C930...
Page 82: Mir4: Power Down Length Count [22:16] (Pdlc)
Middle byte of the free running count. count is reset only when the reset pin is asserted. Timer resolution is 31.25 s when PMX1/2 has a frequency of 32.768 kHz. Description Most significant byte of the free running count. Am79C930...
Page 83: Mir8: Flash Wait States
CLKIN input that is greater than 20 MHz in frequency. This information is needed in order to insure that the TAI section of the Am79C930 device is not pushed beyond design limits. Specifically, when CLKGT20 is set to 1, then the CLKIN signal is divided by 2 before being fed to the TAI section.
Page 84 1 and writing a 0 to this bit has no effect. If the STSCHGFN bit of TCR15 has been set to a 1, then STSCHGD is reset to a 0 automatically whenever the WAKEUP bit of the Am79C930 Number Of Wait States Used By...
Page 85: Mir10: Reserved
0, then the value that is written to this bit will be inverted and driven to the STSTCHG pin of the Am79C930 device. The value that is read from this bit always represents the inverse of the current value of the STSTCHG pin of the Am79C930 device.
Page 86: Transceiver Attachment Interface Registers (Tir Space)
TIRs for each of the system interface modes for each of the two mapping schemes, as well as the address for each register as it appears in the memory map of the 80188 embedded core. Am79C930...
Page 87 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh Am79C930 ISA Plug 80188 Core and Play Address in I/O Address Memory IOBA+0008h mem 400h IOBA+0009h mem 401h IOBA+000Ah mem 402h IOBA+000Bh mem 403h IOBA+000Ch...
Page 88 P R E L I M I N A R Y EIOW = 1 is only allowed while operating in PCMCIA mode. TIR uses 32 I/O addresses: SIR1[1:0] (TAI Bank Select) Am79C930 80188 Core PCMCIA Address in I/O Address Memory...
Page 89: Tir0: Network Control
Multi-Function Pin section. TAI reset. Active high. Asserting this bit will reset the TAI portion of the Am79C930 device, except for this register (i.e., TIR0). Software Strobe. This bit is intended for software development use.
Page 90: Tir2: Serial Device
Multi-Function Pin section. Serial Device Data Tristate. When SDDT is set to 1, the SDDATA pin of the Am79C930 device is tri-stated. When SDDT is set to 0, the SDDATA pin is driven with the value of the SDD bit.
Page 91: Tir3: Fast Serial Port Control
This bit is reset to 0 when the RXRES bit of TIR16 is set to 1, or if a 1 is written to ANTSW. Am79C930 2 X tA 20138B-8...
Page 92: Tir5: Interrupt Register
TXDONE will be set to a 1 when the last data bit for the frame has been sent. CRC Start. CRCS will be set to a 1 by the Am79C930 device when the first bit of the CRC is being transmitted. If the NO TX CRC option has been set, then CRCS will not become set.
Page 93: Tir6: Interrupt Unmask Register 1
ALOKI indicates the cessation of antenna diversity activity so that the incoming network signal can be tracked and decoded by the DPLL. ALOKI will be set to a 1 by the Am79C930 device when the conditions for stopping the antenna diversity switching as set up in...
Page 94: Tir8: Transmit Control
(TIR9) to indicate the state of transmit. Resetting this bit to 0 during transmission will not cause the current transmission to be aborted. Transmission abort is performed with the TXRES bit. Am79C930 byte that follows the last bit of the Start of Transmitted CRC...
Page 95: Tir10: Tx Fifo Data Register
A TXFC value of “0h” indicates a full TX FIFO, i.e., 0 spaces are available. TX Busy. This bit is set to 1 by the Am79C930 device when the transmit operation begins and remains set until the transmission has completed. Specifically, the TXBSY bit will be active whenever...
Page 96 LLOCKE/SA15 pin, depending upon the values of the LLOCKEN bit (TCR14[6]), and the operating mode of the Am79C930 device (i.e., PCMCIA or ISA). The value read from LLOCKE will always represent the current value of the LLOCKE/SA15 pin. The control of the function of the LLOCKE/SA15 pin is described in the Multi-Function Pin section.
Page 97: Tir12: Byte Count Register Lsb
80188 controller will be generated if the RXBCNT interrupt has been unmasked. During RX, the byte counter counts all bytes that follow the Start of Frame Delimiter. Byte count limit FIFO operations. Am79C930 effect state machine...
Page 98: Tir16: Receiver Control
CRC was good. CRC8 Good. The CRC8 machine has detected a good CRC and has latched the byte count that was active at the time that the CRC was good. Am79C930...
Page 99: Tir18: Rx Fifo Data Register
RXFC value of “Fh” indicates a full RX FIFO. RX Busy. This bit is set to 1 by the Am79C930 device when the RXS bit of TIR16 is set to a one, and remains set until the RXRES bit of TIR16 is set to a one, or until any other global reset is activated (e.g., RESET pin of Am79C930 asserted or the CORESET bit of...
Page 100: Tir22: Crc8 Correct Byte Count Lsb
Start of Frame Delimiter and including the CRC bytes are included in the CRC8 Correct Count value, but the bytes that are included in the CRC8 calculation are dependent upon the setting of the PFL bits of TCR3. Am79C930...
Page 101: Tir24: Tcr Index Register
Channel Busy. The Am79C930 device will set this bit to a 1 when the clear channel assessment logic determines that a carrier is pre- sent. The Am79C930 device will set this bit to a 0 when the clear channel assessment logic determines that a carrier is not present.
Page 102: Tir27: Serial Approximation Register
A/D circuit. Description Conversion Active. When an A/D conversion is being performed, the Am79C930 device will set this bit to a 1. When the conversion operation has completed, the Am79C930 device will reset this bit to a 0. Serial Approximation Register. Contains the A/D converter’s Serial Approximation Register value.
Page 103: Tir28: Rssi Lower Limit
RSSI Equal or Above Limit. When the converted RSSI input value equals or exceeds the value in the RSSI lower limit register, then the Am79C930 device will set this bit to a 1. When the converted RSSI input value is less than the value in the RSSI lower limit regis- ter, then the Am79C930 device will set this bit to a 0.
Page 104: Tir31: Test
Start Delimiter. The value in this register determines the number of bytes of preamble that will be verified before the start of frame detect indication is asserted during frame reception and transmission. The following interpretations have been assigned to these bits. Am79C930...
Page 105 TXDLC[1:0] Transmit Data Pin Control. These bits are used to control the state of the TXDL pin when no transmit activity is present. The following interpretations have been assigned to these bits: TXDC[1:0] Am79C930 Programmed Register None TCR10 TCR9, TCR10...
Page 106: Tcr2: Clock Recovery
Physical layer Field Length [3:0]. These bits are used to determine the number of bytes of PHY header that are allowed to pass before the Am79C930 device begins calculating the CRC8 and CRC32 and DC bias control. The Physical layer Field Length value is used...
Page 107: Tcr4: Antenna Diversity Timer
40 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 1 . Am79C930...
Page 108: Tcr6: Tx Ramp Down Timing
The control of the function of the USER6/IRQ5 pin is described in the Multi-Function Pin section. USER5 Function. USER5FN, the PCMCIA mode pin, USER5EN (TCR15[2]), and ISA PnP registers 70h and 71h are used to deter- mine the function of the USER5/IRQ4 pin. Am79C930...
Page 109 ISA Plug and Play configuration software. When this procedure is followed, then the system designer can be assured that the IRQ12 function will not be used by the Am79C930 device, and therefore, the USER1/IRQ12 pin will remain in the high-imped- ance state and will be available for connection to an interrupt gener- ating source in the design.
Page 110: Tcr8: Start Delimiter Lsb
SDLT LSB, bit 0, being checked against the first bit to arrive at the Am79C930 (RX case) or the first bit to leave the Am79C930 (TX case) and continuing in that order.
Page 111: Tcr11: Interrupt Register 3
(TCR0). Start of Frame detection is performed on the bits in the or- der that they appear on the medium, with the SDLT LSB, bit 0, being checked against the first bit to arrive at the Am79C930 (RX case) or the first bit to leave the Am79C930 (Tx case) and continuing in that order.
Page 112: Tcr14: Pin Configuration B
LLOCKE output values are determined by the LLOCKE bit of TIR11. When LLOCKEN is reset to a 0, then the LLOCKE pin is forced to a high- impedance state. Reads of the LLOCKE bit of TIR11 will yield the Am79C930...
Page 113: Tcr15: Pin Configuration C
PnP interrupt level select register, the ISA PnP interrupt type regis- ter, and the PCMCIA pin are used to determine the function of the USER6IRQ5 pin. The control of the function of the USER6/IRQ5 pin is described in the Multi-Function Pin section. Am79C930...
Page 114: Tcr16: Baud Detect Start
0 and a resolution equal to 40 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 1 . Am79C930...
Page 115: Tcr17: Baud Detect Lower Limit
20, 40, 60, 80, etc. CLKIN periods (with CLKGT20=0 each baud tick is one CLKIN period, with CLKGT20=1, each baud tick is two CLKIN periods) will all yield a rising edge baud counter value of 20. The same is true for the falling Am79C930...
Page 116: Tcr19: Baud Detect Accept Count For Carrier Sense
The value in this register is treated as a radix 2 positive real number with two decimal places. The lowest practi- cal value possible is 0.25 (=00.01) and the highest prac- tical value is 3.75 (=11.11). Am79C930...
Page 117: Tcr22: Baud Detect Accept Count
This is a read-only register. measure of the time of RSSI sample relative to the an- tenna switching event. A register value of 0 means that no RSSI samples will be taken. Am79C930...
Page 118: Tcr25: Rssi Configuration
ENEXT is used in conjunction with ENSAR (TCR25[5]) and ADDA (TIR26[2]) to configure the Am79C930 device A/D mode according to the table listed in section RSSI A/D Unit . Enable SAR. Setting ENSAR to a 1 enables the SAR[6:0] pins to drive as outputs.
Page 119 Minimum value in the A2DT[3:0] field must be 0001. A value of 0000 is not allowed. ADT[5:0]=TCR4[5:0] 2 X tA 1 X tA 6 X tA 6 X tA when CLKGT20 = 0 Am79C930 3 X tA SS[5:0]=TCR24[5:0] A2DT[3:0]=TCR25[3:0]+4 X tA 3 X tA 3 X tA 20138B-9...
Page 120: Tcr26: Reserved
TXMOD output will be low assert, such that when the TGAP2 counter expires, the TXMOD pin will be driven to a LOW logic level. When this bit is set to a 1, then the polarity of the TXMOD output will Am79C930...
Page 121: Tcr28: Clear Channel Assessment Configuration
CHBSYC interrupt of TIR4 (bit 7) and the BCF interrupt bit of TIR5. When ENXCHBSY is set to a 1, then antenna diversity switching is disabled and the receive function of the Am79C930 device must be enabled by a positive indication of SDF on the USER6/IRQ5 input pin.
Page 122: Tcr29: Reserved
DR bits of TCR30. When set to a 1, the TXC pin functions as an input, allowing the data rate of the transmit operations to be set by an external source. When TXCIN is set to 1, Am79C930...
Page 123: Tcr31: Device Revision
16-bit deep serial FIFO is inserted into the TX data path. This FIFO allows for some mismatch to be tolerated in the clock rates between the Am79C930 internal transmit clock and the external TXC clock that is connected to the TXC input. Because of this inter-...
Page 124: Pcmcia Ccr Registers And Pcmcia Cis Space
Configuration Option Registers: Description Resets Am79C930 device. Setting this bit to 1 places the Am79C930 device into the reset state, which is equivalent to the as- sertion of the PCMCIA RESET signal. This bit does not reset itself back to 0.
Page 125: Pcmcia Card Information Structure (Cis)
P R E L I M I N A R Y When written with a 1, the PWRDWN bit generates an interrupt to the 80188, requesting that the 80188 core place the Am79C930 de- vice into the power down state. The interrupt is signaled in MIR0, bit 5.
Page 126: Absolute Maximum Ratings
Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. DC CHARACTERISTICS 5.0 V Am79C930 DC Characteristics Parameter Symbol Parameter Description Input LOW Voltage...
Page 127 DC CHARACTERISTICS (continued) 5.0 V Am79C930 DC Characteristics Parameter Symbol Parameter Description IDDPD2 Power Supply Current IDDPD3 Power Supply Current Input Pin Capacitance I/O or Output Pin Capacitance CCLK BCLK Pin Capacitance Notes: 1. I OL1 = 4mA applies to the following pins: STSCHG , PWRDWN, MA[16:0], MD[7:0], FCE, SCE, XCE, MOE, MWE, TDO, LFPE , LFCLK, LLOCKE, HFPE, INPACK, HFCLK, ANTSLT, ANTSLT, TXCMD, TXCMD, TXPE, TXDATA, TXDATA, TXMOD, RXPE, FDET, SDCLK, SDDATA, SDSEL [3:1], SAR[6:0], USER[4:2], USER[0], TXC, ADIN1, ADIN2.
Page 128: 3.3 V Am79C930 Dc Characteristics
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. 3.3 V Am79C930 DC CHARACTERISTICS Parameter Symbol Parameter Description Input LOW Voltage...
Page 129 DC CHARACTERISTICS (continued) 3.3 V Am79C930 DC Characteristics Parameter Symbol Parameter Description IDDPD2 Power Supply Current IDDPD3 Power Supply Current Input Pin Capacitance I/O or Output Pin Capacitance CCLK BCLK Pin Capacitance Notes: 1. I OL1 = 2.4mA applies to the following pins: STSCHG , PWRDWN, MA[16:0], MD[7:0], FCE, SCE, XCE, MOE, MWE, TDO, LFPE , LFCLK, LLOCKE, HFPE, INPACK, HFCLK, ANTSLT, ANTSLT, TXCMD, TXCMD, TXPE, TXDATA, TXDATA, TXMOD, RXPE, FDET, SDCLK, SDDATA, SDSEL [3:1], SAR[6:0], USER[4:2], USER[0], TXC, ADIN1, ADIN2.
Page 130: Ieee 1149.1 Dc Characteristics (5.0 And 3.3 V)
VDD = 5.5 V, VI = 2.7 V VOUT = 0.4 V VOUT = VDD Am79C930 ....0 C to + 70 C DDU1...
Page 131: Absolute Maximum Ratings
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
Page 132: Pcmcia Memory Write Access
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
Page 133: Pcmcia I/O Read Access
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
Page 134: Pcmcia I/O Write Access
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
Page 135: And 3.3 V Isa Interface Ac Characteristics
CL = 50 pF unless otherwise noted Operating ranges define those limits between which the func- tionality of the device is guaranteed. Am79C930 ....0 C to + 70 C...
Page 136: Isa Access
Host performs ISA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory. ISA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access. Host performs ISA READ cycle immediately following completion of ISA WRITE cycle.
Page 137: Memory Bus Interface Ac Characteristics
2 wait states Notes 1, 2 Note 1 Note 2 Note 2 Am79C930 ....0 C to + 70 C DDU1 DDU2 4.75 V to 5.25 V .
Page 138: Memory Bus Write Access
2 wait states 0 wait states 1 wait state 2 wait states TCLKIN-10 Note 1 TCLKIN-10 Note 1, 2 0 wait states 1 wait state 2 wait states Note 2 TCLKIN-15 Note 2 2 X TCLKIN-10 Am79C930 Unit –10 2 X TCLKIN+10...
Page 139: Memory Bus Interface Ac Characteristics
2 wait states Notes 1, 2 Note 1 Note 2 Note 2 Am79C930 ....0 C to + 70 C DDU1 DDU2 3.0 V to 5.25 V .
Page 140: Memory Bus Write Access
2 wait states 0 wait states 1 wait state 2 wait states TCLKIN-10 Note 1 TCLKIN-10 Note 1, 2 0 wait states 1 wait state 2 wait states Note 2 TCLKIN-15 Note 2 2 X TCLKIN-10 Am79C930 Unit –10 2 X TCLKIN+10...
Page 141: Tai Interface Ac Characteristics
CL = 50 pF unless otherwise noted Operating ranges define those limits between which the func- tionality of the device is guaranteed. Am79C930 ....0 C to + 70 C...
Page 142: V Tai Interface Ac Characteristics
Notes 1, 8 Notes 1, 8 Notes 2, 7 Notes 2, 7 Notes 2, 7 Notes 2, 8 Notes 2, 8 Note 6 Note 6 Notes 1, 3 Notes 2, 4 Notes 2, 4 Notes 2, 3 Am79C930 Unit TCLTX-165 TCHTX...
Page 143 P R E L I M I N A R Y t RXDS min = 110–CLKP X T CLKIN t RXDH min = 10+CLKP X T CLKIN t RXDS min = 110–CLKP X T CLKIN X 2 t RXDH min = 10+CLKP X T CLKIN X 2 Am79C930...
Page 144: Tai Interface Ac Characteristics
CL = 50 pF unless otherwise noted Operating ranges define those limits between which the func- tionality of the device is guaranteed. Am79C930 ....0 C to + 70 C...
Page 145 RXDS min = 110–CLKP X T CLKIN t RXDH min = 10+CLKP X T CLKIN t RXDS min = 110–CLKP X T CLKIN X 2 t RXDH min = 10+CLKP X T CLKIN X 2 Am79C930 Unit 1000 1000...
Page 146: And 3.3 V User Programmable Pins Ac Characteristics
Operating ranges define those limits between which the func- tionality of the device is guaranteed. Test Conditions Note 1 Note 1 Am79C930 ....0 C to + 70 C DDU1 DDU2 3.0 V to 5.25 V...
Page 147: And 3.3 V Ieee 1149.1 Interface Ac Characteristics
Note 1 7 bits 4 bits 1.25 to 1.75 V** 0 to (ADREF x 2) Am79C930 ....0 C to + 70 C DDU1 DDU2 3.0 V to 5.25 V...
Page 148: Timing Waveforms
ELWH t ELWL t WLWH t AVWL t WLWTV t WTLWTH t GHWL t DVWH t WLQZ t GHQZ Am79C930 t GHAX t GHEH t GHQZ t QVWTH 20138B-10 t WMAX t GHEH t WHGL t WTHWH t WMDX...
Page 149 Figure 7. PCMCIA I/O WRITE Access Timing Diagram t IGLIGH t WTHQV t WTLWTH t IGLQV t IGQNZ tI WHAX t IWHRGH tI WHEH t IWLIWH tWTHIWH t WTLWTH t IWHDX Am79C930 t IGHAX t IGHRGH t IGHEH t IGHIAH t IGHQX t IGHQZ 20138B-12 20138B-13...
Page 150: Isa Bus Interface Waveforms
8 t i 20 t i 21 t i 34 t i 11 Figure 8. ISA All Access Timing Diagram Am79C930 t i 12 t i 23 t i 31 t i 13 t i 22 t i 16...
Page 151: Memory Bus Interface Waveforms
WD t m WP t m WQ t m SW valid t m CQ t m CV Am79C930 t m AH t m AD t m CD t m CH t m OD t m HZ t m RDHC...
Page 152: Clock Waveforms
CLTX 2.0 V t CHTX 0.8 V t TXLH t TXHL t TXC t CLRX 2.0 V t CHRX 0.8 V t RXLH t RXHL t RXC Figure 11. CLOCK Timing Diagram Am79C930 0.8 V 0.8 V 0.8 V 20138B-17...
Page 153: Tai Waveforms
P R E L I M I N A R Y t n 1 t n 2 t n 3 t n 4 Figure 12. TAI Timing Diagram t RXDS t RXDS t TXDD t TXDV t TXDS t TXDH Figure 13. Serial Data Timing Diagram Am79C930 20138B-18 20138B-19...
Page 154: Programmable Interface Waveforms
(data change) RCO** (drive change) RCO** (drive change) **RCO = Register Controlled Output Figure 14. Programmable Interface Timing Diagram P R E L I M I N A R Y t u 1 t u 2 t u 3 Am79C930 20138B-20...
Page 155: Ieee 1149.1 Interface Waveforms
TDI, TMS Output Signals Input Signals P R E L I M I N A R Y t 25 t 30 t 31 t 32 t 34 t 36 t 37 Figure 15. IEEE 1149.1 Timing Diagram Am79C930 t 35 20138B-21...
Page 156: Ac Test Reference Waveforms
PCMCIA power supply pins are set to 5.0 V (i.e., VDDP pins = 5.0 V). measured parameter value the PCMCIA power supply pins are set to 3.3 V (i.e., VDDP pins = 3.3 V). measured parameter value Am79C930 20138B-22 20138B-23...
Page 157: 5.0 V Non-Pcmcia Ac Test Reference Waveform
PCMCIA bus interface. measured parameter value Interface signals, IEEE 1149.1 signals and any other signal not considered to be part of the PCMCIA bus interface. measured parameter value Am79C930 20138B-24 20138B-25...
Page 158: Physical Dimensions
Copyright 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. PCnet is a trademark of AMD. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Page 159: Appendix A: Typical Am79C930 System Application
The general function of the Am79C930 device is to pro- vide the MAC layer functions for an IEEE 802.11 (draft) or Xircom Netwave protocol network. The following sec-...
Page 160: Frame Transmission
FIFO. As the RX FIFO becomes filled with data, it will re- quest that data be removed by asserting the DMA chan- nel 0 input of the Am79C930 80188 core. The 80188 core will move the received data from the RX FIFO into the SRAM data buffer space and will examine the desti- nation address.
Page 161 Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet- FAST , PCnet- FAST +, PCnet-Mobile, QFEX, QFEXr, QuASI , QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc.

AMD Am79C930 Preliminary Manual

Distinctive Characteristics

General Description

Ordering Information

Block Diagram

Pcmcia Block Diagram

Pcmcia Connection Diagram

Pcmcia Pin Summary

Pcmcia Pin List

Pcmcia Pin Function Summary

Isa Plug and Play Block Diagram

Connection Diagram

Isa Plug and Play Pin List

Isa Plug and Play Pin Summary

Pin Descriptions

Functional Description

Amd

Register Descriptions

Notes

Amd

Absolute Maximum Ratings

Operating Ranges

DC Characteristics

Absolute Maximum Ratings

Operating Ranges

Ac Characteristics

Pcmcia Memory Read Access

Pcmcia Memory Write Access

Pcmcia I/O Read Access

Pcmcia I/O Write Access

And 3.3 V Isa Interface Ac Characteristics

Isa Access

Memory Bus Interface Ac Characteristics

Memory Bus Read Access

Memory Bus Write Access

Memory Bus Interface Ac Characteristics

Memory Bus Read Access

Memory Bus Write Access

Tai Interface Ac Characteristics

Tai Interface Ac Characteristics

And 3.3 V User Programmable Pins Ac Characteristics

And 3.3 V Ieee 1149.1 Interface Ac Characteristics

Analog-To-Digital (A/D) Converter Characteristics

Amd

Timing Waveforms

Clock Waveforms

Tai Waveforms

Programmable Interface Waveforms

Ieee 1149.1 Interface Waveforms

Ac Test Reference Waveforms

Physical Dimensions

APPENDIX A: Typical Am79C930 System Application

Quick Links

DISTINCTIVE CHARACTERISTICS

GENERAL DESCRIPTION

Summary of Contents for AMD Am79C930