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AC CHARACTERISTICS
5.0 AND 3.3 V PCMCIA INTERFACE
ABSOLUTE MAXIMUM RATINGS
Storage Temperature:
. . . . . . . . . . . .
Ambient Temperature Under Bias:
Supply Voltage to AVSS
or DVSS (AVDD, DVDD):
. . . . . . . . . . . . . .
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
PCMCIA MEMORY READ ACCESS
Parameter
Symbol
Parameter Description
tAVQV
Address access time
Address setup to OE
tAVGL
Address hold from OE
tGHAX
CE access time
tELQV
CE setup to OE
tELGL
CE hold from OE
tGHEH
CE hold from WE
OE acess time
tGLQV
WAIT valid from OE
tGLWTV
WAIT pulse width
tWTLWTH
Data Bus driven from OE
tGLQNZ
Data setup to WAIT
tQVWTH
Data disabled from OE
tGHQZ
Notes:
1. Assumes no wait state access is programmed.
2. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
FLASH and SRAM wait states set at "3."
1
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
4
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
6
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto
memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
3. Parameter is not included in production test.
P R E L I M I N A R Y
OPERATING RANGES
Commercial (C) Devices
Temperature (T
Supply Voltages (V
–65 to +150*C
. . .
–65 to +125*C
Supply Voltages
(AV
–0.3 to +6 V
All inputs within the range: V
V
for a given input pin. (See section on power supply
pin descriptions.)
CL = 50 pF unless otherwise noted
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Test Conditions
Note 1
Note 1
(READ) or
(WRITE)
Note 1
Notes 2, 3
Note 3
Note 3
Am79C930
)
. . . . . . . . . . . . . . . . .
A
, V
CC
DDT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
, V
)
. . . . . . . . . . . . . . . . . . . . . . . .
DD
DD5
– where V
and V
are appropriate reference pins
DD
SS
DD
Min
0
5
20
0
0
20
0
0
0
AMD
0 C to + 70 C
, V
, V
, V
, V
)
DDU1
DDU2
DDM
DDP
3.0 V to 5.25 V
+5 V
– 0.5 V V
V
+ 0.1 X
SS
IN
DD
Max
Unit
550
ns
ns
ns
550
ns
ns
ns
200
ns
35
ns
53 X TCLKIN
ns
ns
ns
90
ns
131
5%
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