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AMD Am188 ES Manuals
Manuals and User Guides for AMD Am188 ES. We have
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AMD Am188 ES manual available for free PDF download: User Manual
AMD Am188 ES User Manual (192 pages)
Brand:
AMD
| Category:
Microcontrollers
| Size: 1.42 MB
Table of Contents
Table of Contents
5
Design Philosophy
13
Intended Audience
13
Preface
13
Purpose of this Manual
13
User's Manual Overview
13
Amd Documentation
14
E86 Family
14
Introduction and Overview
13
Chapter 1 Features and Performance
15
Key Features and Benefits
15
Distinctive Characteristics
16
Figure 1-1 Am186Es Microcontroller Block Diagram
18
Figure 1-2 Am188Es Microcontroller Block Diagram
19
Application Considerations
20
Clock Generation
20
Memory Interface
20
Figure 1-3 Basic Functional System Design
20
Chapter 2 Programming
23
Register Set
23
Processor Status Flags Register
24
Figure 2-1 Register Set
24
Figure 2-2 Processor Status Flags Register (F)
24
Memory Organization and Address Generation
25
Figure 2-3 Physical Address Generation
26
Figure 2-4 Memory and I/O Space
26
I/O Space
26
Instruction Set
26
Table 2-1 Instruction Set
27
Data Types
30
Segments
30
Table 2-2 Segment Register Selection Rules
30
Figure 2-5 Supported Data Types
31
Addressing Modes
32
Table 2-3 Memory Addressing Mode Examples
32
Chapter 3 System Overview
33
Bus Operation
52
Figure 3-1 Am186Es Microcontroller Address Bus-Normal Read and
53
Figure 3-2 Am186Es Microcontroller-Read and Write with Address Bus
53
Figure 3-3 Am188Es Microcontroller Address Bus-Normal Read
54
Figure 3-4 Am188Es Microcontroller-Read and Write with Address
54
Bus Interface Unit
55
Nonmultiplexed Address Bus
55
Static Bus Sizing
55
Byte Write Enables
56
Pseudo Static RAM (PSRAM) Support
56
Table 3-3 Programming Am186Es Microcontroller Bus Width
56
Clock and Power Management Unit
57
Phase-Locked Loop (PLL)
57
Crystal-Driven Clock Source
57
Figure 3-5 Oscillator Configurations
58
External Source Clock
59
System Clocks
59
Power-Save Operation
59
Figure 3-6 Clock Organization
59
Chapter 4 Peripheral Control Block
61
Figure 4-5 System Configuration Register
62
Figure 7-17 End-Of-Interrupt Register
62
Table 4-1 Peripheral Control Block Register Map
62
Peripheral Control Block Relocation Register
63
(RELREG, Offset Feh)
63
Figure 4-1 Peripheral Control Block Relocation Register
63
Figure 4-2 Reset Configuration Register
64
Reset Configuration Register (RESCON, Offset F6H)
64
Figure 4-3 Processor Release Level Register
65
Processor Release Level Register (PRL, Offset F4H)
65
Table 4-2 Processor Release Level (PRL) Values
65
Auxiliary Configuration Register (AUXCON, Offset F2H)
66
Figure 4-4 Auxiliary Configuration Register
66
System Configuration Register (SYSCON, Offset F0H)
67
Initialization and Processor Reset
68
Table 4-3 Initial Register State after Reset
69
Pin Descriptions
33
Table 3-1 Numeric PIO Pin Designations
45
Table 3-2 Alphabetic PIO Pin Designations
46
Pins that Are Used by Emulators
51
Overview
61
Chapter 5 Chip Select Unit
71
Overview
71
Table 5-1 Chip Select Register Summary
71
Chip Select Timing
72
Ready and Wait-State Programming
72
Chip Select Overlap
72
Chip Select Registers
73
Upper Memory Chip Select Register (UMCS, Offset A0H)
74
Figure 5-1 Upper Memory Chip Select Register
74
Table 5-2 UMCS Block Size Programming Values
74
Low Memory Chip Select Register (LMCS, Offset A2H)
76
Figure 5-2 Low Memory Chip Select Register
76
Table 5-3 LMCS Block Size Programming Values
76
Midrange Memory Chip Select Register (MMCS, Offset A6H)
78
Figure 5-3 Midrange Memory Chip Select Register
78
PCS and MCS Auxiliary Register (MPCS, Offset A8H)
80
Figure 5-4 PCS and MCS Auxiliary Register
80
Table 5-4 MCS Block Size Programming
80
Peripheral Chip Select Register (PACS, Offset A4H)
82
Figure 5-5 Peripheral Chip Select Register
82
Table 5-5 PCS Address Ranges
83
Table 5-6 PCS3-PCS0 Wait-State Encoding
83
Chapter 6 Refresh Control Unit
85
Overview
85
Memory Partition Register (MDRAM, Offset E0H)
85
Figure 6-1 Memory Partition Register
85
Clock Prescaler Register (CDRAM, Offset E2H)
86
Enable RCU Register (EDRAM, Offset E4H)
86
Figure 6-2 Clock Prescaler Register
86
Figure 6-3 Enable RCU Register
86
Watchdog Timer Control Register (WDTCON, Offset E6H)
87
Figure 6-4 Watchdog Timer Control Register
87
Table 6-1 Watchdog Timer COUNT Settings
88
Table 6-2 Watchdog Timer Duration
88
Chapter 7 Interrupt Control Unit
89
Overview
89
Definitions of Interrupt Terms
89
Table 7-1 Am186Es and Am188Es Microcontroller Interrupt Types
92
Interrupt Conditions and Sequence
93
Interrupt Priority
94
Software Exceptions, Traps, and NMI
95
Interrupt Acknowledge
96
Figure 7-1 External Interrupt Acknowledge Bus Cycles
96
Interrupt Controller Reset Conditions
97
Master Mode Operation
98
Fully Nested Mode
98
Figure 7-2 Fully Nested (Direct) Mode Interrupt Controller Connections
98
Cascade Mode
99
Figure 7-3 Cascade Mode Interrupt Controller Connections
99
Special Fully Nested Mode
100
Operation in a Polled Environment
100
End-Of-Interrupt Write to the EOI Register
100
Master Mode Interrupt Controller Registers
101
Table 7-2 Interrupt Controller Registers in Master Mode
101
INT0 and INT1 Control Registers
102
(I0CON, Offset 38H, I1CON, Offset 3Ah)
102
Figure 7-4 INT0 and INT1 Control Registers
102
INT2 and INT3 Control Registers
103
(I2CON, Offset 3Ch, I3CON, Offset 3Eh)
103
Figure 7-5 INT2 and INT3 Control Registers
103
Figure 7-6 INT4 Control Register
104
INT4 Control Register (I4CON, Offset 40H)
104
Figure 7-7 Timer/Dma Interrupt Control Registers
105
Timer and DMA Interrupt Control Registers (TCUCON, Offset 32H, DMA0CON/INT5CON, Offset 34H, DMA1CON/INT6CON, Offset 36H)
105
Serial Port 0/1 Interrupt Control Registers
106
(SP0CON/SP1CON, Offset 44H/42H)
106
Figure 7-8 Serial Port 0/1 Interrupt Control Register
106
Table 7-3 Priority Level
106
Figure 7-9 Interrupt Status Register
107
Interrupt Status Register (INTSTS, Offset 30H)
107
Figure 7-10 Interrupt Request Register
108
Interrupt Request Register (REQST, Offset 2Eh)
108
Figure 7-11 Interrupt In-Service Register
110
Interrupt In-Service Register (INSERV, Offset 2Ch)
110
Figure 7-12 Priority Mask Register
111
Priority Mask Register (PRIMSK, Offset 2Ah)
111
Table 7-4 Priority Level
111
Figure 7-13 Interrupt Mask Register
112
Interrupt Mask Register (IMASK, Offset 28H)
112
Figure 7-14 Poll Status Register
113
Poll Status Register (POLLST, Offset 26H)
113
Figure 7-15 Poll Register
114
Poll Register (POLL, Offset 24H)
114
End-Of-Interrupt Register (EOI, Offset 22H)
115
Figure 7-16 Example EOI Assembly Code
115
Slave Mode Operation
116
Slave Mode Interrupt Nesting
116
Slave Mode Interrupt Controller Registers
116
Table 7-5 Interrupt Controller Registers in Slave Mode
116
Timer and DMA Interrupt Control Registers
117
Figure 7-18 Timer and DMA Interrupt Control Registers
117
Interrupt Status Register (INTSTS, Offset 30H)
118
Figure 7-19 Interrupt Status Register
118
Interrupt Request Register (REQST, Offset 2Eh)
119
Figure 7-20 Interrupt Request Register
119
Interrupt In-Service Register (INSERV, Offset 2Ch)
120
Figure 7-21 Interrupt In-Service Register
120
Priority Mask Register (PRIMSK, Offset 2Ah)
121
Table 7-6 Priority Level
121
Interrupt Mask Register (IMASK, Offset 28H)
122
Specific End-Of-Interrupt Register (EOI, Offset 22H)
123
Interrupt Vector Register (INTVEC, Offset 20H)
124
Chapter 8 Timer Control Unit
125
Overview
125
Pulse Width Demodulation
125
Programmable Registers
126
Timer Operating Frequency
126
Table 8-1 Timer Control Unit Register Summary
126
Timer 0 and Timer 1 Mode and Control Registers (T0CON, Offset 56H, T1CON, Offset 5Eh)
127
Timer 2 Mode and Control Register (T2CON, Offset 66H)
129
Timer Count Registers (T0CNT, Offset 50H, T1CNT, Offset 58H, T2CNT, Offset 60H)
130
Timer Maxcount Compare Registers (T0CMPA, Offset 52H, T0CMPB, Offset 54H, T1CMPA, Offset 5Ah, T1CMPB, Offset 5Ch, T2CMPA, Offset 62H)
131
Chapter 9 Dma Controller
133
Overview
133
Dma Operation
133
Table 9-1 DMA Controller Register Summary
133
Programmable Dma Registers
135
DMA Control Registers (D0CON, Offset Cah, D1CON, Offset Dah)
135
Table 9-2 Synchronization Type
136
Serial Port/Dma Transfers
137
DMA Transfer Count Registers (D0TC, Offset C8H, D1TC, Offset D8H)
138
DMA Destination Address High Register (High Order Bits) (D0DSTH, Offset C6H, D1DSTH, Offset D6H)
139
DMA Destination Address Low Register (Low Order Bits) (D0DSTL, Offset C4H, D1DSTL, Offset D4H)
140
DMA Source Address High Register (High Order Bits) (D0SRCH, Offset C2H, D1SRCH, Offset D2H)
141
DMA Source Address Low Register (Low Order Bits) (D0SRCL, Offset C0H, D1SRCL, Offset D0H)
142
Dma Requests
143
Table 9-3 Maximum DMA Transfer Rates
143
Synchronization Timing
144
DMA Acknowledge
145
DMA Priority
145
DMA Programming
145
DMA Channels on Reset
146
Chapter 10 Asynchronous Serial Ports
147
Overview
147
Serial Port Flow Control
147
Table 10-1 Serial Port External Pins
148
Programmable Registers
149
Table 10-2 Asynchronous Serial Port Register Summary
150
Serial Port 0/1 Control Registers (SP0CT/SP1CT, Offset 80H/10H)
151
Table 10-3 DMA Control Bits
151
Table 10-4 Serial Port MODE Settings
153
Serial Port 0/1 Status Registers (SP0STS/SP1STS, Offset 82H/12H)
155
Serial Port 0/1 Transmit Registers (SP0TD/SP1TD, Offset 84H/14H)
157
Serial Port 0/1 Receive Registers (SP0RD/SP1RD, Offset 86H/16H)
158
Serial Port 0/1 Baud Rate Divisor Registers (SP0BAUD/SP1BAUD, Offset 88H/18H)
159
Table 10-5 Common Baud Rates
159
Chapter 11 Programmable I/O Pins
161
Overview
161
Table 11-1 PIO Pin Assignments
162
Pio Mode Registers
163
PIO Mode 1 Register (PIOMODE1, Offset 76H)
163
PIO Mode 0 Register (PIOMODE0, Offset 70H)
163
Table 11-2 PIO Mode and PIO Direction Settings
163
Pio Direction Registers
164
PIO Direction 1 Register (PDIR1, Offset 78H)
164
PIO Direction 0 Register (PDIR0, Offset 72H)
164
Pio Data Registers
165
Open-Drain Outputs
165
Register Summary
167
Table A-1 Internal Register Summary
167
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