AMD AMD5K86 x86 Processor Manuals

Manuals and User Guides for AMD AMD5K86 x86 Processor. We have 1 AMD AMD5K86 x86 Processor manual available for free PDF download: Technical Reference

AMD AMD5K86 Technical Reference (412 pages)

Brand: AMD | Category: Processor | Size: 24 MB

Table of Contents
3
Overview
21
Features
22
Internal Architecture
25
FIGURE 2-1. Internal Architecture, with Pipeline Stage
26
Prefetch and Predecode
27
Execution Pipeline
28
FIGURE 2-2. Pipeline Stage Functions
29
Fetch
30
Decode
31
Execute
32
Integer/Shift Units
33
TABLE 2-1. ALU Instruction Classes
33
Floating-Point Unit
34
Result
35
Retire
36
Cache Organization and Management
37
Instruction Cache
38
Data Cache
39
Cache Tags
40
Cache-Line Fills
41
Cache Coherency
42
TABLE 2-2. Cache States for Read and Write Accesses
43
TABLE 2-3. Cache States for Snoops, Invalidation, and Replacements
44
Snooping
45
TABLE 2-4. Snoop Action
46
Internal Snooping
46
Buffers
47
Prefetch Cache
48
Replacement and Invalidation Writeback Buffer
49
Snoop Writeback Buffer
50
Read/Write Reordering
51
Paging and the Tlbs
52
Software Environment and Extensions
55
FIGURE 3-1. Control Register 4 (CR4)
56
TABLE 3-1. Control Register 4 (CR4) Fields
57
Machine-Check Exceptions
58
Mbyte Pages
59
FIGURE 3-2. 4-Kbyte Paging Mechanism
59
FIGURE 3-3. 4-Mbyte Paging Mechanism
60
TABLE 3-2. Page-Directory Entry (PDE) Fields
62
Global Pages
63
FIGURE 3-5. Page-Table Entry (PTE)
64
TABLE 3-3. Page-Table Entry (PTE) Fields
65
Virtual-8086 Mode Extensions (VME)
66
Hardware Interrupts and the VIF and VIP Extensions
67
FIGURE 3-6. EFLAGS Register
69
TABLE 3-4. Virtual-Interrupt Additions to EFLAGS Register
69
TABLE 3-5. Instructions that Modify the if or VIF Flags
70
Bitmap (IRB) Extension
75
FIGURE 3-7. Task State Segment (TSS)
76
TABLE 3-6. Interrupt Behavior and Interrupt-Table Access
77
Protected Virtual Interrupt (PVI) Extensions
78
FIGURE 3-8. Machine-Check Address Register (MCAR)
79
Model-Specific Registers (Msrs)
79
FIGURE 3-9. Machine-Check Type Register (MCTR)
80
TABLE 3-7. Machine-Check Type Register (MCTR) Fields
81
Time Stamp Counter (TSC)
81
Hardware Configuration Register (HWCR)
82
Cpuid
83
Cmpxchg8B
86
MOV to and from CR4
87
Rdtsc
88
RDMSR and WRMSR
89
Illegal Instruction (Reserved Opcode)
92
Performance
93
Dispatch and Execution Timing
97
TABLE 4-1. Integer Instructions
100
Integer Dot Product Example
109
TABLE 4-2. Integer Dot Product Internal Operations Timing
110
TABLE 4-3. Floating-Point Instructions
111
Bus Interface
119
FIGURE 5-1. Signal Groups
120
TABLE 5-1. Summary of Signal Characteristics
120
Signal Overview
120
Signal Characteristics
122
Conditions for Driving and Sampling Signals
126
- TABLE 5-2. Conditions for Driving and Sampling Signals
  127
- External Interrupts
  132
- TABLE 5-3. Summary of Interrupts and Exceptions
  135
- Bus Signal Compatibility with Pentium Processor
  136
- A20M (Address Bit 20 Mask)
  137
- A31–A3 (Address Bus)
  139
- TABLE 5-4. Address-Generation Sequence During Bursts
  140
- ADS (Address Strobe)
  143
- ADSC (Address Strobe Copy)
  146
- AHOLD (Address Hold)
  147
- AP (Address Parity)
  150
- APCHK (Address Parity Check)
  151
- BE7–BE0 (Byte Enables)
  152
- TABLE 5-5. Relation of BE7-BE0 to Other Signals
  153
- TABLE 5-6. Encodings for Special Bus Cycles
  154
- BF (Bus Frequency)
  155
- TABLE 5-7. Processor-To-Bus Clock Ratios
  155
- BOFF (Backoff)
  156
- TABLE 5-8. Outputs Floated When BOFF Is Asserted
  157
- BRDY (Burst Ready)
  160
- RDYC (Burst Ready)
  163
- BREQ (Bus Request)
  164
- BUSCHK (Bus Check)
  165
- CACHE (Cacheable Access)
  168
- TABLE 5-9. MESI-State Transitions for Reads
  170
- CLK (Bus Clock)
  171
- D/C (Data or Code)
  172
- D63–D0 (Data Bus)
  174
- TABLE 5-10. Relation between D63-D0, BE7-BE0, and DP7-DP0
  175
- DP7–DP0 (Data Parity)
  176
- EADS (External Address Strobe)
  177
- EWBE (External Write Buffer Empty)
  181
FERR (Floating-Point Error)
183
FLUSH (Cache Flush)
185
FRCMC (Functional-Redundancy Check Master/Checker)
188
HIT (Inquire-Cycle Hit)
190
TABLE 5-11. MESI-State Transitions for Inquire Cycles
191
HITM (Inquire Cycle Hit to Modified Line)
192
TABLE 5-12. Outputs Floated When HLDA Is Asserted
194
HLDA (Bus-Hold Acknowledge)
194
HOLD (Bus-Hold Request)
196
IERR (Internal Error)
198
IGNNE (Ignore Numeric Error)
199
INIT (Initialization)
200
INTR (Maskable Interrupt)
203
TABLE 5-13. Interrupt Acknowledge Operation Definition
204
INV (Invalidate Cache Line)
207
KEN (External Cache Enable)
208
LOCK (Bus Lock)
210
M/IO (Memory or I/O)
214
NA (Next Address)
215
NMI (Non-Maskable Interrupt)
216
PCD (Page Cache Disable)
218
PCHK (Parity Status)
220
PEN (Parity Enable)
221
PRDY (Probe Ready)
222
TABLE 5-14. PWT, Writeback/Writethrough, and MESI
224
PWT (Page Writethrough)
224
R/S (Run or Stop)
226
RESET (Reset)
228
TABLE 5-15. Register State after RESET or INIT
229
TABLE 5-16. Outputs at RESET
231
SCYC (Split Cycle)
233
SMI (System Management Interrupt)
235
SMIACT (System Management Interrupt Active)
240
STPCLK (Stop Clock)
241
TCK (Test Clock)
246
TDI (Test Data Input)
247
TDO (Test Data Output)
248
TMS (Test Mode Select)
249
TRST (Test Reset)
250
W/R (Write or Read)
251
WB/WT (Writeback or Writethrough)
252
TABLE 5-17. MESI-State Transitions for Reads
253
TABLE 5-18. MESI-State Transitions for Writes
254
TABLE 5-19. Bus Cycle Definitions
255
Bus Cycle Overview
255
Addressing
256
Alignment
257
Bus Speed and Typical DRAM Timing
258
Bus Cycle Timing
259
Single-Transfer Reads and Writes
260
FIGURE 5-2. Single-Transfer Memory Read and Write
262
Single-Transfer Memory Write Delayed by EWBE Signal
263
FIGURE 5-3. Single-Transfer Memory Write Delayed by
264
FIGURE 5-4. I/O Read and Write
265
TABLE 5-20. Bus-Cycle Order During Misaligned Transfers
266
Single-Transfer Misaligned Memory and I/O Transfers
266
FIGURE 5-5. Single-Transfer Misaligned Memory and
267
Burst Cycles
268
TABLE 5-21. Address-Generation Sequence During Bursts
269
FIGURE 5-6. Burst Reads
270
FIGURE 5-7. Burst Read (NA Sampled)
271
Burst Writeback
272
FIGURE 5-8. Burst Writeback Due to Cache-Line Replacement
274
Bus Arbitration and Inquire Cycles
275
AHOLD-Initiated Inquire Miss
276
FIGURE 5-9. AHOLD-Initiated Inquire Miss
277
FIGURE 5-10. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
278
AHOLD-Initiated Inquire Hit to Modified Line
279
FIGURE 5-11. AHOLD-Initiated Inquire Hit to Modified Line
280
Bus Backoff (BOFF)
281
FIGURE 5-12. Basic BOFF Operation
282
BOFF-Initiated Inquire Hit to Modified Line
283
FIGURE 5-13. BOFF-Initiated Inquire Hit to Modified Line
284
HOLD-Initiated Inquire Hit to Shared or Exclusive Line
285
FIGURE 5-14. HOLD-Initiated Inquire Hit to Shared or Exclusive Line
286
FIGURE 5-15. HOLD-Initiated Inquire Hit to Modified Line
287
Locked Cycles
288
FIGURE 5-16. Basic Locked Operation
289
TLB Miss (4-Kbyte Page)
290
FIGURE 5-17. TLB Miss (4-Kbyte Page)
291
Locked Operation with BOFF Intervention
292
FIGURE 5-18. Locked Operation with BOFF Intervention
293
TABLE 5-22. Interrupt Acknowledge Operation Definition
294
TABLE 5-23. Encodings for Special Bus Cycles
299
FIGURE 5-20. Basic Special Bus Cycle (Halt Cycle)
300
FIGURE 5-21. Shutdown Cycle
301
FIGURE 5-22. FLUSH-Acknowledge Cycle
302
FIGURE 5-23. Cache-Invalidation Cycle (INVD Instruction)
303
FIGURE 5-24A. Cache-Writeback and Invalidation Cycle
304
FIGURE 5-24B. Cache-Writeback and Invalidation Cycle
305
TABLE 5-24. Branch-Trace Message Special Bus Cycle Fields
306
FIGURE 5-25. Branch-Trace Message Cycle
307
Mode Transitions, Reset, and Testing
308
Stop-Grant and Stop-Clock States
311
Real Mode
314
FIGURE 5-28. INIT-Initiated Transition from Protected Mode to Real Mode
315
System Design
317
Memory Map
318
FIGURE 6-1. Typical Desktop-System BIOS Memory Map
319
Memory-Decoder Aliasing of Boot ROM Space
320
SMM Memory Space and Cacheability
321
FIGURE 6-2. Default SMM Memory Map
323
Cache
324
L2 Cache
325
Writethrough Vs. Writeback Coherency States
326
Inquire Cycles
328
Bus Arbitration for Inquire Cycles
330
BOFF Arbitration
331
FIGURE 6-3. BOFF Example
332
AHOLD Arbitration
333
FIGURE 6-4. AHOLD and BOFF Example
334
HOLD Arbitration
335
FIGURE 6-5. Write-Once Protocol
337
Cache Invalidations
338
System Management Mode (SMM)
339
Operating Mode and Default Register Values
340
TABLE 6-1. Initial State of Registers in SMM
341
SMM State-Save Area
341
TABLE 6-2. SMM State-Save Area Map
342
SMM Revision Identifier
344
Halt Restart Slot
346
I/O Trap Dword
347
Exceptions and Interrupts in SMM
348
SMM Compatibility with Pentium Processor
349
State Transitions
350
FIGURE 6-6. Clock Control State Transitions
352
Stop Grant State
353
- Stop Clock State
  354
- Clock Design
  356
- FIGURE 6-8. CLK Delay Function
  357
- FIGURE 6-9. CLK Synthesizer with Output Enable
  358
- FIGURE 6-10. CPUCLK Clamping Circuit
  358
- Noise Reduction
  359
- Thermal Design
  360
- Design Support and Peripheral Products
  361
- Test and Debug
  363
- FIGURE 7-1. Hardware Configuration Register (HWCR)
  365
- TABLE 7-1. Hardware Configuration Register (HWCR) Fields
  366
- Built-In Self Test (BIST)
  367
- TABLE 7-2. bist Error Bit Definition in EAX Register
  368
- Test Access Port (TAP) bist
  368
- Output-Float Test
  369
- FIGURE 7-2. Array Access Register (AAR)
  370
- TABLE 7-3. Array Ids in Array Pointers
  371
- Array Pointer
  371
- FIGURE 7-3. Test Formats: Data-Cache Tags
  372
- Array Test Data
  372
- FIGURE 7-4. Test Formats: Data-Cache Data
  373
- FIGURE 7-5. Test Formats: Instruction-Cache Tags
  374
- FIGURE 7-6. Test Formats: Instruction-Cache Instructions
  375
- FIGURE 7-7. Test Formats: 4-Kbyte TLB
  376
- FIGURE 7-8. Test Formats: 4-Mbyte TLB
  377
- Debug Registers
  378
- Debug Compatibility with Pentium Processor
  379
- Functional-Redundancy Checking
  380
- Boundary-Scan Test Access Port (TAP)
  381
- Device Identification Register
  383
- Public Instructions
  384
- Hardware Debug Tool (HDT)
  385
- A.1 Bus Signals
  388
- A.2 Bus Interface
  391
- A.2.3 Bus Cycle Order of Misaligned Memory and I/O Cycles
  392
- Comments
  393
- A.3 Bus Mastering Operations (Including Snooping)
  394
- Comments
  395
- A.3.6 Write Hit to a Shared Line in the DCACHE
  396
- A.4 Memory Management
  397
- A.5 Power Saving Features
  398
- A.5.5 NMI Recognition During SMM
  399
- A.6 Exceptions
  400
- A.7 Debug
  401

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AMD AMD5K86 x86 Processor Manuals

AMD AMD5K86 Technical Reference (412 pages)

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