Isa Access - AMD Am79C930 Preliminary Manual

Am79c930 pcnettm-mobile single-chip wireless lan media access controller
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ISA ACCESS

Parameter
Symbol
Parameter Description
ti1
LA[23:17] valid setup to BALE
ti2
BALE
ti3
LA[23:17] valid hold from BALE
LA[23:17] valid setup to CMD
ti4
SA[16:0] valid setup to CMD
ti7
CMD
ti8
ti9
SA[16:0] valid setup to BALE
Data valid delay from RCMD
ti10
Data valid setup to WCMD
ti11
SA[16:0] valid hold from CMD
ti12
CMD
ti13
Data valid hold from RCMD
ti14
Data valid hold from WCMD
ti15
Data disabled from RCMD
ti16
ti20
IOCHRDY
ti21
IOCHRDY
pulse width
CMD
ti22
ti23
BALE
ti25
Data valid delay from IOCHRDY
LA[23:17] valid hold from CMD
ti26
AEN valid setup to CMD
ti30
AEN valid hold from CMD
ti31
ti32
AEN valid setup to BALE
Data enabled from RCMD
ti34
Notes:
1. CMD = one of: MEMR , MEMW , IOR or IOW .
2. RCMD = one of: MEMR , or IOR .
3. WCMD = one of: MEMW , or IOW .
4. If no wait states are incurred.
5. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
FLASH and SRAM wait states set at "3."
1
Host performs ISA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
ISA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
Host performs ISA READ cycle immediately following completion of ISA WRITE cycle.
4
After completion of first embedded 80188 access to FLASH, posted ISA WRITE executes to SRAM;
ISA READ stycle is being held in wait state.
5
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
6
After completion of second embedded 80188 access to FLASH, ISA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to ISA bus and wait state is exited.
6. Parameter is not included in production test.
7. Parameter only applies when IOCHRDY is deasserted.
136
P R E L I M I N A R Y
to BALE
pulse width
to CMD
pulse width
to CMD
pulse width
delay from CMD
to IOCHRDY
delay from IOCHRDY
delay from CMD
Test Conditions
Note 1
Note 1
Note 4
Notes 2, 5, 6
Note 3
Note 1
Note 1
Note 2
Note 3
Note 2, 6
Notes 1, 7
Notes 5, 6, 7
Notes 1, 7
Note 1
Note 7
Note 1
Note 1
Note 1
Notes 2, 4
Am79C930
Min
Max
60
25
12
80
25
6*TCLKIN
20
53 X TCLKIN
–75
20
55
0
20
20
60
0
130 +
53 X TCLKIN
35
20
–TCLKIN
25
–15
80
15
60
0
110
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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