Samsung STH-N271 Service Manual page 61

11. STH-N271 Circuit Description & Circuit Diagrams
STH-N271 provides the AMPS and the Digital TDMA (cellular band only) of compliance with TIA/EIA-137.
The radio operation of the STH-N271 has been implemented with the receiver, the transmitter, and the local
oscillator controlled by the PLL. The circuit of the STH-N271 is described as followings.
1. Baseband Section
1-1. Power Supply
For the POWER ON, with the battery installed on the telephone and by pressing the END key, the BATT
and ON_SW signals will be connected, which it will turn on Q107. In addition, Q106 is turned on by Q107,
and thus the BATT is connected to VBAT. Consequently, VBAT is supplied to input of regulators U110 and
U111. The regulator U110 supplies all powers of baseband part (VCC, AVCC, V_VCTCXO). The regulator
U111 supplies IVCC (2.2 V) to Baseband Engine Chip (U203: BEC). The BEC (U203), which is supplied
power from VCC, IVCC and reference clock 14.4 MHz from TCXO (OSC302), will start to run. If BEC will
start to run normally, the BEC output POWER_HOLD signal (low active) which is connected to Q105.
Moreover, Q105, Q107 and Q106 are turned on in order. In consequence, BATT is connected to VBAT
continuously. Although END key is released (ON_SW disconnected BATT). The power from U110 and
U111 is used in all baseband part of BEC, IFC (Interface Chip U101).
For the POWER OFF, in this case main application program is running already. The main application
program is checking all GPIO inputs periodically. When press the END key during program is running, the
BATT and ON_SW signals will be connected. This turns on Q107. Therefore, ON_SW_SENSE that is
connected to GPIO_0_5 (U203_ C13) turned logic high to low. The BEC checks this signal, main application
program enter to POWER OFF mode.
1-2. BEC (U203) interface
The BEC (U203) is mainly consist of two parts HOST CPU and Baseband Engine (Figure2-1). This is an
important component of dual-mode (US-TDMA and AMPS mode) cellular phone. It has 1Kx 32 of internal
ROM and 2Kx32 of internal RAM. This is communicate with a lot of peripheral device, memory (Flash
ROM, SRAM), Key Pad and LCD. The BEC receives TCXO clock signals from the TCXO and controls the
phone during the operation. The BEC communicates with the IFC through several serial links. These
include CODEC, wideband data, receiver data, transmitter data, and auxiliary data interface Signals. A
master baseband clock (BBCLK: U203_H2) at either 6.2208 MHz or 5.12 MHz or 4.096 MHz, depending on
the operating mode, from the BEC drives the IFC. The major components are as follows:
Separate address and data buses provide a data path to external memory and memory mapped
peripherals. The 22-bit address bus provides a byte addressing range up to 8 MB in each of 4 spaces
decoded by the 4 select signals. The 16-bit data bus in conjunction with the UBE signal allows word or byte
transfers. Table2-1 shows the ARM memory map. An Intel 28F3204 Stacked Memory chip supplies 4M
Bytes of Flash memory and 512 KBytes of SRAM. Note that in the phone, the SRAM is located at the
CS_RES1 block of memory.
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