Operating Sequences; Figure 6: Power-On Sequence Diagram (No Pin Code Activated); This Document Is The Sole And Exclusive Property Of Wavecom. Not To Be Distributed Or Divulged Without Prior Written; Agreement - Wavecom Integra M2106+ Product Specification

3.3.2

Operating Sequences

3.3.2.1 Power-ON
®
Once the Wireless CPU
(Hold delay on the ON/~OFF signal) to power-ON.
After this delay, once the firmware has completed its power-up sequence, an internal logic maintains the
®
Wireless CPU in power ON condition.
You must not de-assert this ON/~OFF signal before this internal logic is internally asserted by the firmware;
®
the Wireless CPU would not start-up otherwise
PO W ER SUPPLY
IN T ERN A L RST
STA T E OF TH E
W ireles s CPU

Figure 6: Power-ON sequence diagram (no PIN code activated)

The duration of the firmware power-up sequence depends on several factors:
• firmware version used by the Wireless CPU
• need to perform a recovery sequence if the power has been lost during a flash memory modification.
Other factors have a minor influence
• number of parameters stored in EEPROM by the AT commands received so far
• ageing of the hardware components, especially the flash memory
• temperature conditions
The recommended way to de-assert the ON/~OFF signal is to use either an AT command or WIND
indicators: the application must detect the end of the power-up initialization and de-assert ON/~OFF
afterwards.
• Send an "AT" command and wait for the "OK" answer: once the initialization is complete the AT
interface answers « OK » to "AT" message
• Wait for the "+WIND: 3" message: after initialization, the Wireless CPU
return an unsolicited "+WIND: 3" message. The generation of this message is enabled or disabled via
1
If the application manages hardware flow control, an AT command can be sent during the initialisation phase.
©Confidential

This document is the sole and exclusive property of Wavecom. Not to be distributed or divulged without prior written

agreement.

WA_DEV_M2106+_PTS_003-001
is supplied the ON/~OFF signal must be asserted high during a delay of T
ON / ~ OFF
®
W ireles s CPU
O FF
®
®
,
1
.
T
on -h old
T
rs t
(4 2 m s t y p )
W ireles s CPU
RESET m od e
ON
(n o lo c . u p d at e)
SIM an d N et w ork d ep en d en t
Integra M2106+
Erreur ! Style non défini.
on-hold
A T an sw ers « O K »
® ®
W ireles s CPU
REA D Y
®
, if configured to do so, will
Page: 25 / 77
April, 2007