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+3V3D
VIDEO BUSES
1. Progressive Mode: 10 Bit Y/C on 20 bit wide bus
Vaddis V Output
Function
SiI9190 Input
C1143
VIDP19..12
Y9..2
D15..8
100N
VIDP11..10
Y1..0
D3..2
50V
VIDP9..2
C9..2
D23..16
0805
VIDP1..0
C1..0
D7..6
(C = multiplexed CbCr data)
2. Interlaced Mode: 8 Bit multiplexed YCbCr
Vaddis V Output
Function
SiI9190 Input
VIDP7..0
YC7..0
D15..8
VIDP[0..19]
VIDP[0..19]
1=Prog scan, 0=Interlaced
IC1100A
P1130
PROG/INT*
1
PROG/INT*
OE
VIDP7
2
A0
VIDP6
4
A1
+3V3D
VIDP5
6
A2
VIDP4
8
A3
R1114
74LVC244APW
10K
TSSOP-20
0805
IC1100B
P1131
19
OE
TR1102
VIDP19
17
A0
MMUN2211LT1
VIDP18
15
A1
SOT-23
VIDP17
13
A2
VIDP16
11
A3
74LVC244APW
DGND
TSSOP-20
IC1101A
1
OE
VIDP3
2
A0
VIDP2
4
A1
VIDP1
6
A2
VIDP0
8
A3
74LVC244APW
TSSOP-20
IC1101B
19
OE
VIDP15
17
A0
VIDP14
15
A1
VIDP13
13
A2
VIDP12
11
A3
74LVC244APW
TSSOP-20
+3V3D
C1134
C1135
C1136
C1137
C1138
100N
100N
100N
100N
100N
16V
16V
16V
16V
16V
0603
0603
0603
0603
0603
Around video bus
DGND
+3V3D
IC1100C
IC1101C
IC1103B
20
20
14
VCC
VCC
VCC
C1121
C1111
C1112
C1144
100UF
100N
100N
100N
10V
16V
16V
16V
10
10
7
YXF
GND
GND
GND
0603
0603
0603
74LVC244APW
74LVC244APW
74LV164D
TSSOP-20
TSSOP-20
S0-14
DGND
REG1100
LM1086CS-3.3
+5VD
TO-263
+3V3_HDMI
+3V3
C1116
C1100
10UF
100N
50V
16V
YK
0603
DGND
+3V3D
L1100
120R@100MHz
NF
Option to bypass reg
REG1102
LM1086CS-ADJ
TO-263
+1V8_HDMI
R1100
C1139
Some decoupling
C1142
caps are on
120R
100N
bottom of PCB
0W125
16V
P1134
100UF
0805
0603
10V
BOTTOM
YXF
R1101
56R
+3V3D
0W125
0805
R1105
DGND
10K
HDMI_RESET*
0W125
0805
9190_INT*
DGND
18
RP1100A
1
8
100R
HD15
P1114
P1118
Y0
16
2
7
100R
HD14
P1115
RP1100B
P1119
Y1
14
3
6
100R
HD13
P1116
RP1100C
P1120
Y2
100R
12
P1117
RP1100D
4
5
HD12
P1121
Y3
3
Y0
5
Y1
7
Y2
9
Y3
VSYNC*
100R
18
P1122
RP1101A
1
8
HD11
P1126
Y0
100R
16
RP1101B
2
7
HD10
P1123
P1127
Y1
14
RP1101C
3
6
100R
HD9
P1124
P1128
Y2
CLK27M_VID
12
4
5
100R
HD8
P1125
RP1101D
P1129
Y3
MCLK_HDMI
SPDIF
ABCLK_HDMI
ALRCLK
ADAT0
ADAT1
3
Y0
ADAT2
5
Y1
7
Y2
9
Y3
IC1103A
IC1104A
+3V3D
P1137
1
3
2
DSA
Q0
1I0
1Y
HSYNC*
2
4
3
HSYNC*
DSB
Q1
1I1
5
P1138
Q2
6
5
Q3
2I0
2Y
10
6
Q4
2I1
CLK27M_VID
8
11
CP
Q5
+3V3D
12
11
Q6
3I0
3Y
9
13
10
MR
Q7
3I1
74LV164D
14
4I0
4Y
S0-14
13
4I1
PROG/INT*
1
S
15
EN
74LVC157AD
S0-16
DGND
HSYNC DELAY CIRCUIT
delays HSYNC* by 4 clocks in
progressive mode and 8 clocks in
interlaced mode. This is to ensure
IC1104B
HSYNC and VSYNC falling edges
16
VCC
are coincident as required by HDMI
specification
C1145
100N
16V
8
GND
0603
74LVC157AD
S0-16
L1101
3V3_PVCC2
120R@100MHz
C1117
C1101
C1104
C1122
100UF
100N
100N
1N0
10V
16V
16V
50V
0603
YXF
0603
0603
DGND
L1102
3V3_PVCC1
120R@100MHz
C1118
C1102
C1105
C1123
100UF
100N
100N
1N0
10V
16V
16V
50V
0603
YXF
0603
0603
DGND
+3V3D
L1103
3V3_AVCC
120R@100MHz
C1119
C1103
C1106
C1107
100UF
100N
100N
100N
16V
10V
16V
16V
YXF
0603
0603
0603
BOTTOM
BOTTOM
DGND
C1140
C1141
C1124
C1125
100N
100N
1N0
1N0
16V
16V
50V
50V
0603
0603
0603
0603
BOTTOM
BOTTOM
BOTTOM
DGND
P1133
HDMI_RESET*
42
RESET#
EXT_SWING
P1132
9190_INT*
17
INT
TX2+
TX2-
41
CI2CA
SCL
43
SCL
CSCL
SDA
44
SDA
CSDA
TX1+
TX1-
VIDP9
49
D23
VIDP8
50
D22
VIDP7
51
D21
TX0+
VIDP6
52
D20
TX0-
VIDP5
53
D19
VIDP4
54
D18
VIDP3
55
D17
HDMI TX
TXC+
VIDP2
56
D16
TXC-
HD15
57
D15
HD14
58
D14
SII9030
HD13
61
D13
HPD
HD12
62
D12
HD11
63
D11
TQFP-80
HD10
64
D10
DSCL
HD9
65
D9
DSDA
HD8
67
D8
VIDP1
68
D7
VIDP0
69
D6
70
D5
75
D4
VIDP11
76
D3
VIDP10
77
D2
78
D1
79
D0
DGND
80
DE
VSYNC*
2
VSYNC
HSYNCD*
1
HSYNC
CLK27M_VID
66
IDCK
MCLK_HDMI
6
MCLK
SPDIF
5
SPDIF
ABCLK_HDMI
12
SCK
ALRCLK
11
WS
ADAT0
10
SD0
ADAT1
9
SD1
ADAT2
8
SD2
7
SD3
21
RSVDL
DGND
DGND
P1140
R1104
4
HSYNCD*
P1139
75R 0603
7
9
12
+3V3D
C1120
C1108
C1109
C1110
100UF
100N
100N
100N
10V
16V
16V
16V
YXF
0603
0603
0603
BOTTOM
BOTTOM
IC1102
DGND
R1108
P1101
24
3V3_AVCC
470R 0603
36
35
33
32
30
29
27
26
P1100
18
+3V3D
P1104
HPDIN
20
R1106
R1107
19
HOTPLUG buffer
10K
10K
P1102
0W125
0W125
HPD
0805
0805
TR1100
TR1101
R1109
P1103
1K0
DZ1100
C1127
0W125
MMUN2211LT1
MMUN2211LT1
0805
BZX84C
1N0
SOT-23
SOT-23
5V6
50V
SOT-23
0603
DGND
+3V3D
+5VD
P1136
D1102
R1115
R1102
R1103
27K
0W063
R1116
L1106
2K2
2K2
0603
P1105
P1107
P1109
0W063
0W063
100R
0603
0603
C1113
120R@100MHz
0W063
0603
P1135
27P
BAT54S
100V
SOT-23
0805
To Vaddis
DGND
DGND
CEC
+5VD
D1100
R1110
1K8
0603
R1112
L1104
P1106
P1108
P1110
100R
C1131
120R@100MHz
0W063
NF
0603
27P
BAT54S
100V
SOT-23
0805
To Vaddis
DGND
DGND
DDC_SCL
+5VD
D1101
R1111
1K8
0603
R1113
L1105
P1111
P1112
P1113
100R
C1132
120R@100MHz
0W063
NF
0603
27P
BAT54S
REG1101
SOT-23
100V
L78L05ACD
To Vaddis
DGND
0805
+12VD
SO-8
DGND
8
1
DDC_SDA
+5
C1114
100N
16V
0603
DGND
DRAWING TITLE
DV79 HDMI
Filename:
L974C11.Sch
Notes:
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR
Contact Engineer:
Peter Gaggs
Contact Tel:
(01223) 203270
C1126
DGND
C1129
EMC_GND
1N0
R1117
50V
10N
100R
0603
50V
0603
0603
TX2+
1
SKT1100
2
TX2-
3
MOLEX
TX1+
4
500254
5
TX1-
6
TX0+
7
8
TX0-
9
TXC+
10
11
TXC-
12
CEC_OUT
13
14
DDC_SCL_OUT
15
DDC_SDA_OUT
16
17
+5V_HDMI
18
19
DGND
C1130
C1128
10N
50V
0603
DGND
1N0
50V
EMC_GND
0603
Cable screen capacitively
coupled to chassis to avoid
connecting 0V to chassis via
external equipment
HDMI +5V Power Signal
C1133
C1115
100UF
100N
25V
16V
YK
0603
04_E142
PG
23-09-04
Correct BOM error - R320 now fitted
04_E129
PG
24-08-04
Production release
ECO No.
INITIALS
DATE
DESCRIPTION OF CHANGE
L974C11
Printed:
23-Sep-2004
Sheet
11
of
11
A2
DRAWING NO.
1.1
1.0
ISSUE
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