Sandy Bridge - Ddr Controi - EUROCOM P270WM Service Manual

Sandy Bridge - DDR ControI

M_MAA_A0 CL25
DDR0_MA[00]
M_MAA_A1 CR25
DDR0_MA[01]
CG25
M_MAA_A2
CK24 DDR0_MA[02]
M_MAA_A3
DDR0_MA[03]
M_MAA_A4 CM24
DDR0_MA[04]
M_MAA_A5 CL23
DDR0_MA[05]
CN23
M_MAA_A6
CM22 DDR0_MA[06]
M_MAA_A7
DDR0_MA[07]
M_MAA_A8 CK22
DDR0_MA[08]
CN21
M_MAA_A9
CK26 DDR0_MA[09]
M_MAA_A10
DDR0_MA[10]
M_MAA_A11 CL21
DDR0_MA[11]
M_MAA_A12 CK20
DDR0_MA[12]
CG29
M_MAA_A13
DDR0_MA[13]
M_MAA_A14 CG19
DDR0_MA[14]
M_MAA_A15 CN19
DDR0_MA[15]
12 M_MAA_A[15:0]
M_SBS_A0 CM28
DDR0_BA[0]
M_SBS_A1 CN27
DDR0_BA[1]
M_SBS_A2 CM20
DDR0_BA[2]
12 M_SBS_A[2:0]
CE29
12 M_RAS_A_N DDR0_RAS_N
CL29
12 M_CAS_A_N DDR0_CAS_N
CN29
12 M_WE_A_N
DDR0_WE_N
M_SCS_A_N0 CN25
DDR0_CS_N[0] DDR1_CS_N[0]
CH26
M_SCS_A_N1
CC23 DDR0_CS_N[1] DDR1_CS_N[1]
12 M_SCS_A_N[1:0]
RSVD
CB28
RSVD
CG27
DDR0_CS_N[4] DDR1_CS_N[4]
CF26
CB26 DDR0_CS_N[5] DDR1_CS_N[5]
RSVD
CC25
RSVD
CL27
RSVD
CK28
RSVD
CH24
12 CK_M_CH0_0_DP DDR0_CLK_DP[0] DDR1_CLK_DP[0]
CF24
12 CK_M_CH0_0_DN
DDR0_CLK_DN[0] DDR1_CLK_DN[0]
CG23
DDR0_CLK_DP[1] DDR1_CLK_DP[1]
CE23
DDR0_CLK_DN[1] DDR1_CLK_DN[1]
CG21
12 CK_M_CH0_2_DP DDR0_CLK_DP[2] DDR1_CLK_DP[2]
CE21
12 CK_M_CH0_2_DN
DDR0_CLK_DN[2] DDR1_CLK_DN[2]
CH22
DDR0_CLK_DP[3] DDR1_CLK_DP[3]
CF22
DDR0_CLK_DN[3] DDR1_CLK_DN[3]
CL19
12 M_SCKE_A0
DDR0_CKE[0]
CM18
12 M_SCKE_A1 DDR0_CKE[1]
CH20
CP18 DDR0_CKE[2]
DDR0_CKE[3]
CF20
RSVD
CE19
RSVD
CE25
12 M_ODT_A0
DDR0_ODT[0]
CE27
12 M_ODT_A1 DDR0_ODT[1]
CH28
CF28 DDR0_ODT[2]
DDR0_ODT[3]
CB24
RSVD
CC27
RSVD
CM26
RSVD
CC21
RSVD
10 OF 17
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DC23 M_MAA_B0
DDR1_MA[00]
DE23 M_MAA_B1
DDR1_MA[01]
DF24
M_MAA_B2
DDR1_MA[02] DA23
M_MAA_B3
DDR1_MA[03]
DB22 M_MAA_B4
DDR1_MA[04]
DF22 M_MAA_B5
DDR1_MA[05]
DE21
M_MAA_B6
DDR1_MA[06] DF20
M_MAA_B7
DDR1_MA[07]
DB20 M_MAA_B8
DDR1_MA[08]
DA19
M_MAA_B9
DDR1_MA[09] DF26
M_MAA_B10
DDR1_MA[10]
DE19 M_MAA_B11
DDR1_MA[11]
DC19 M_MAA_B12
DDR1_MA[12]
DB30
M_MAA_B13
DDR1_MA[13]
DB18 M_MAA_B14
DDR1_MA[14]
DC17 M_MAA_B15
DDR1_MA[15]
M_MAA_B[15:0] 13 14 M_MAA_C[15:0]
DB26 M_SBS_B0
DDR1_BA[0]
DC25 M_SBS_B1
DDR1_BA[1]
DF18 M_SBS_B2
DDR1_BA[2]
M_SBS_B[2:0] 13 14 M_SBS_C[2:0]
DB28
DDR1_RAS_N M_RAS_B_N 13 14 M_RAS_C_N
CY30
DDR1_CAS_N M_CAS_B_N 13 14 M_CAS_C_N
CV28
M_WE_B_N 13 14 M_WE_C_N
DDR1_WE_N
DB24 M_SCS_B_N0
CU23
M_SCS_B_N1
CR23
M_SCS_B_N[1:0] 13 14 M_SCS_C_N[1:0]
RSVD
CR27
RSVD
CU25
CT24
DA29
RSVD
CT26
RSVD
CR21
RSVD
DA27
RSVD
CY20
CK_M_CH1_0_DP 13 14 CK_M_CH2_0_DP
CV20
CK_M_CH1_0_DN 13 14 CK_M_CH2_0_DN
CY22
CV22
CV24
CK_M_CH1_2_DP 13 14 CK_M_CH2_2_DP
CY24
CK_M_CH1_2_DN 13 14 CK_M_CH2_2_DN
DC21
DA21
CT20
M_SCKE_B0 13 14 M_SCKE_C0
DDR1_CKE[0]
CU19
DDR1_CKE[1] M_SCKE_B1 13 14 M_SCKE_C1
CY18
DDR1_CKE[2] DA17
DDR1_CKE[3]
CR19
RSVD
CT18
RSVD
CT22
M_ODT_B0 13 14 M_ODT_C0
DDR1_ODT[0]
DA25
DDR1_ODT[1] M_ODT_B1 13 14 M_ODT_C1
CY26
DDR1_ODT[2] CV26
DDR1_ODT[3]
CU27
RSVD
CY28
RSVD
DE25
RSVD
CU21
RSVD
U31J
M_MAA_C0 AB18 A19 M_MAA_D0
DDR2_MA[00] DDR3_MA[00]
M_MAA_C1 R19 E21 M_MAA_D1
DDR2_MA[01] DDR3_MA[01]
U19 F20
M_MAA_C2 M_MAA_D2
T20 DDR2_MA[02] DDR3_MA[02] B20
M_MAA_C3 M_MAA_D3
DDR2_MA[03] DDR3_MA[03]
M_MAA_C4 P20 D20 M_MAA_D4
DDR2_MA[04] DDR3_MA[04]
M_MAA_C5 U21 A21 M_MAA_D5
DDR2_MA[05] DDR3_MA[05]
R21 F22
M_MAA_C6 M_MAA_D6
P22 DDR2_MA[06] DDR3_MA[06] B22
M_MAA_C7 M_MAA_D7
DDR2_MA[07] DDR3_MA[07]
M_MAA_C8 T22 D22 M_MAA_D8
DDR2_MA[08] DDR3_MA[08]
R23 G23
M_MAA_C9 M_MAA_D9
T18 DDR2_MA[09] DDR3_MA[09] D18
M_MAA_C10 M_MAA_D10
DDR2_MA[10] DDR3_MA[10]
M_MAA_C11 U23 A23 M_MAA_D11
DDR2_MA[11] DDR3_MA[11]
M_MAA_C12 T24 E23 M_MAA_D12
DDR2_MA[12] DDR3_MA[12]
R15 A13
M_MAA_C13 M_MAA_D13
DDR2_MA[13] DDR3_MA[13]
M_MAA_C14 W25 D24 M_MAA_D14
DDR2_MA[14] DDR3_MA[14]
M_MAA_C15 U25 F24 M_MAA_D15
DDR2_MA[15] DDR3_MA[15]
M_SBS_C0 R17 A17 M_SBS_D0
DDR2_BA[0] DDR3_BA[0]
M_SBS_C1 L17 E19 M_SBS_D1
DDR2_BA[1] DDR3_BA[1]
M_SBS_C2 P24 B24 M_SBS_D2
DDR2_BA[2] DDR3_BA[2]
U17 B16
DDR2_RAS_N DDR3_RAS_N
T16 B14
DDR2_CAS_N DDR3_CAS_N
P16 A15
DDR2_WE_N DDR3_WE_N
M_SCS_C_N0 AB20 G19 M_SCS_D_N0
DDR2_CS_N[0] DDR3_CS_N[0]
AE19 J19
M_SCS_C_N1 M_SCS_D_N1
AD16 DDR2_CS_N[1] DDR3_CS_N[1] F14
RSVD RSVD
AA15 G15
RSVD RSVD
AA19 K18
DDR2_CS_N[4] DDR3_CS_N[4]
P18 G17
AB16 DDR2_CS_N[5] DDR3_CS_N[5] F16
RSVD RSVD
Y16 E15
RSVD RSVD
W17 D16
RSVD RSVD
AA17 K16
RSVD RSVD
AB24 L23
DDR2_CLK_DP[0] DDR3_CLK_DP[0]
Y24 J23
DDR2_CLK_DN[0] DDR3_CLK_DN[0]
AB22 L21
DDR2_CLK_DP[1] DDR3_CLK_DP[1]
Y22 J21
DDR2_CLK_DN[1] DDR3_CLK_DN[1]
AA21 K20
DDR2_CLK_DP[2] DDR3_CLK_DP[2]
W21 M20
DDR2_CLK_DN[2] DDR3_CLK_DN[2]
AA23 M22
DDR2_CLK_DP[3] DDR3_CLK_DP[3]
W23 K22
DDR2_CLK_DN[3] DDR3_CLK_DN[3]
AA25 K24
DDR2_CKE[0] DDR3_CKE[0]
T26 M24
DDR2_CKE[1] DDR3_CKE[1]
U27 J25
AD24 DDR2_CKE[2] DDR3_CKE[2] N25
DDR2_CKE[3] DDR3_CKE[3]
AE25 R25
RSVD RSVD
AE23 R27
RSVD RSVD
Y20 L19
DDR2_ODT[0] DDR3_ODT[0]
W19 F18
DDR2_ODT[1] DDR3_ODT[1]
AD18 E17
Y18 DDR2_ODT[2] DDR3_ODT[2] J17
DDR2_ODT[3] DDR3_ODT[3]
AD22 D14
RSVD RSVD
AE21 M16
RSVD RSVD
M18 B18
RSVD RSVD
AD20 G21
RSVD RSVD
11 OF 17
1554653-1 U31K
Sandy Bridge - DDR ControI B - 5
Schematic Diagrams
Sheet 4 of 63
M_MAA_D[15:0] 15
Sandy Bridge -
M_SBS_D[2:0] 15 DDR Control
M_RAS_D_N 15
M_CAS_D_N 15
M_WE_D_N 15
M_SCS_D_N[1:0] 15
CK_M_CH3_0_DP 15
CK_M_CH3_0_DN 15
CK_M_CH3_2_DP 15
CK_M_CH3_2_DN 15
M_SCKE_D0 15
M_SCKE_D1 15
M_ODT_D0 15
M_ODT_D1 15