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Fujitsu MB15F74UL Datasheet page 9

Dual serial input pll frequency synthesizer
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• Programmable Counter
(LSB)
1
2
3
4
SW
/
IF
CN1 CN2 LDS
RF
A1 to A7
N1 to N11
LDS
SW
/
IF
RF
FC
/
IF
RF
CN1, 2
Note : Data input with MSB first.
(2) Data setting
Binary 14
bit Programmable Reference Counter Data Setting
-
Divide ratio
R14 R13 R12 R11 R10 R9
3
0
0
4
0
0
16383
1
1
Note : Divide ratio less than 3 is prohibited.
Binary 11
bit Programmable Counter Data Setting
-
Divide ratio N11 N10 N9
3
0
0
4
0
0
2047
1
1
Note : Divide ratio less than 3 is prohibited
Binary 7
bit Swallow Counter Data Setting
-
Divide ratio
A7
A6
0
0
0
1
0
0
127
1
1
Data Flow
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
FC
/
IF
A1 A2 A3 A4 A5 A6 A7
RF
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: LD/fout signal select bit
: Divide ratio setting bit for the prescaler (IF : SW
: Phase control bit for the phase detector (IF : FC
: Control bit
R8
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
N8
N7
N6
N5
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
, RF : SW
IF
, RF : FC
IF
R7
R6
R5
R4
R3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
N4
N3
N2
N1
0
0
1
1
0
1
0
0
1
1
1
1
MB15F74UL
(MSB)
23
)
RF
)
RF
R2
R1
1
1
0
0
1
1
9

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