Page 1
DESCRIPTION The Fujitsu MB15F74UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the 2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
MB15F74UL (Continued) • Direct power saving function : Power supply current in power saving mode Typ 0.1 A (V 3.0 V, Ta 25 C) Max 10 A (V 3.0 V) • Software selectable charge pump current : 1.5 mA/6.0 mA Typ •...
MB15F74UL PIN DESCRIPTION Pin no. Descriptions name Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling. Prescaler complimentary input for the IF-PLL section. Xfin This pin should be grounded via a capacitor. Ground pin for the IF-PLL section. Power supply voltage input pin for the IF-PLL section (except for the charge pump CCIF circuit) , the shift register and the oscillator input buffer.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
MB15F74UL ELECTRICAL CHARACTERISTICS 2.7 V to 3.6 V, Ta 40 C to 85 C) Value Parameter Symbol Condition Unit 2000 MHz CCIF *1 3.0 V CCIF Power supply current 2500 MHz CCRF 3.0 V CCRF “L” PSIF Power saving current “L”...
Page 7
MB15F74UL (Continued) 2.7 V to 3.6 V, Ta 40 C to 85 C) Value Parameter Symbol Condition Unit 3.0 V, CS bit “H” “H” level output IF *8 DOH *4 Vp 2, current CS bit “L” 25 C 3.0 V, CS bit “H”...
MB15F74UL FUNCTIONAL DESCRIPTION 1. Pulse swallow function [ (P : Output frequency of external voltage controlled oscillator (VCO) : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL) : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) : Preset divide ratio of binary 7-bit swallow counter (0 127, A <...
Page 9
MB15F74UL • Programmable Counter (LSB) Data Flow (MSB) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CN1 CN2 LDS A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) N1 to N11...
Page 10
MB15F74UL Prescaler Data Setting • Divide ratio “H” “L” Prescaler divide ratio IF-PLL 32/33 64/65 Prescaler divide ratio RF-PLL 64/65 128/129 • Charge Pump Current Setting Current value 6.0 mA 1.5 mA fout output Selectable Bit Setting • LD/fout pin state LD output fout output...
Page 11
MB15F74UL 3. Power Saving Mode (Intermittent Mode Control Circuit) Status PS pin Normal mode Power saving mode The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value.
Page 12
MB15F74UL 4. Serial Data Data Input Timing Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal.
Page 13
MB15F74UL PHASE COMPARATOR OUTPUT WAVEFORM IF RF IF RF (FC bit High) IF RF FC bit Low IF RF • LD Output Logic IF-PLL section RF-PLL section LD output Locking state/Power saving state Locking state/Power saving state Locking state/Power saving state Unlocking state Unlocking state Locking state/Power saving state...
MB15F74UL TYPICAL CHARACTERISTICS fin input sensitivity RF-PLL input sensitivity vs. Input frequency SPEC 2.7 V 3.0 V 3.6 V SPEC 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 [MHz] IF-PLL input sensitivity vs. Input frequency SPEC 2.7 V 3.0 V 3.6 V SPEC...
Page 16
MB15F74UL input sensitivity Input sensitivity vs. Input frequency SPEC 2.7 V 3.0 V 3.6 V SPEC Input frequency f (MHz)
Page 17
MB15F74UL 3. RF-PLL Do output current • 1.5 mA mode 10.0 3.0 V 10.0 Charge pump output voltage V • 6.0 mA mode 10.0 3.0 V 10.0 Charge pump output voltage V...
Page 18
MB15F74UL IF-PLL Do output current • 1.5 mA mode 10.0 3.0 V 10.0 Charge pump output voltage V • 6.0 mA mode 10.0 3.0 V 10.0 Charge pump output voltage V...
MB15F74UL REFERENCE INFORMATION for Lock up Time Phase Noise and Reference Leakage 2500 MHz 3.0 V Test Circuit 50 MHz/V 25 C 200 kHz CP : 6 mA mode S.G. 13 MHz 7.5 k Spectrum To VCO Analyzer 2.7 k 1500 pF 330 pF 15000 pF...
Page 22
MB15F74UL (Continued) PLL Lock Up time PLL Lock Up time 2500 MHz 2550 MHz within 1 kHz 2550 MHz 2500 MHz within 1 kHz L ch H ch 440 s H ch L ch 400 s A Mkr x: 439.99764 s A Mkr x: 400.00146 s y: 50.0009 MHz y: 50.0013 MHz...
MB15F74UL APPLICATION EXAMPLE 1000 pF TCXO From controller GND OSC Clock Data 1000 pF 1000 pF Xfin 1000 pF Xfin MB15F74UL 1000 pF CCIF CCRF 3.0 V 3.0 V 3.0 V 0.1 F LD/fout 3.0 V 0.1 F 0.1 F 0.1 F Output Lock Det.
MB15F74UL USAGE PRECAUTIONS (1) V , Vp and Vp must be equal voltage. CCRF CCIF Even if either RF-PLL or IF-PLL is not used, power must be supplied to V , Vp and Vp to keep CCRF CCIF them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions : Store and transport devices in conductive containers.
Details of "A" part Details of "B" part Details of "C" part Details of "D" part 0.50±0.10 0.50±0.10 0.50±0.10 0.30±0.10 (.020±.004) (.020±.004) (.020±.004) (.012±.004) C0.20(.008) 0.60±0.10 0.30±0.10 0.60±0.10 0.40±0.10 (.024±.004) (.012±.004) (.024±.004) (.016±.004) 2001 FUJITSU LIMITED C20056S-c-2-1 Dimensions in mm ( inches )
Page 26
(2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.