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Pin Description - Fujitsu MB15F74UL Datasheet

Dual serial input pll frequency synthesizer
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PIN DESCRIPTION

Pin
Pin no.
I/O
name
Prescaler input pin for the IF-PLL.
1
fin
I
IF
Connection to an external VCO should be AC coupling.
Prescaler complimentary input for the IF-PLL section.
2
Xfin
I
IF
This pin should be grounded via a capacitor.
3
GND
Ground pin for the IF-PLL section.
IF
Power supply voltage input pin for the IF-PLL section (except for the charge pump
4
V
CCIF
circuit) , the shift register and the oscillator input buffer.
Power saving mode control pin for the IF-PLL section. This pin must be set at "L" when
5
PS
I
the power supply is started up. (Open is prohibited.)
IF
PS
6
Vp
Power supply voltage input pin for the IF-PLL charge pump.
IF
7
Do
O
Charge pump output for the IF-PLL section.
IF
Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The
8
LD/fout
O
output signal is selected by LDS bit in a serial data.
LDS bit
9
Do
O
Charge pump output for the RF-PLL section.
RF
10
Vp
Power supply voltage input pin for the RF-PLL charge pump.
RF
Power saving mode control for the RF-PLL section. This pin must be set at "L" when the
11
PS
I
power supply is started up. (Open is prohibited. )
RF
PS
Power supply voltage input pin for the RF-PLL section (except for the charge pump
12
V
CCRF
circuit)
13
GND
Ground pin for the RF-PLL section
RF
Prescaler complimentary input pin for the RF-PLL section.
14
Xfin
I
RF
This pin should be grounded via a capacitor.
Prescaler input pin for the RF-PLL.
15
fin
I
RF
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
16
LE
I
When LE is set "H", data in the shift register is transferred to the corresponding latch
according to the control bit in a serial data.
Serial data input pin (with the schmitt trigger circuit)
17
Data
I
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref.
counter, RF-prog. counter) according to the control bit in a serial data.
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
18
Clock
I
One bit data is shifted into the shift register on a rising edge of the clock.
The programmable reference divider input pin. TCXO should be connected with an AC
19
OSC
I
IN
coupling capacitor.
20
GND
Ground pin for OSC input buffer and the shift register circuit.
"H" ; Normal mode/PS
IF
IF
"H" ; outputs fout signal/LDS bit
"H" ; Normal mode/PS
RF
Descriptions
"L" ; Power saving mode
"L" ; outputs LD signal
"L" ; Power saving mode
RF
MB15F74UL
3

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